Differential D18516 Diff 50718 autotests/folding/light52_tb.vhdl.fold

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autotests/folding/light52_tb.vhdl.fold

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52	use work.light52_tb_pkg.all;	52	use work.light52_tb_pkg.all;
53	use work.txt_util.all;	53	use work.txt_util.all;
54		54
55	entity <beginfold id='16'>light52_tb</beginfold id='16'> is	55	entity <beginfold id='16'>light52_tb</beginfold id='16'> is
56	generic (BCD : boolean := true);	56	generic (BCD : boolean := true);
57	<endfold id='16'>end;</endfold id='16'>	57	<endfold id='16'>end;</endfold id='16'>
58		58
59		59
60	<beginfold id='5'>architecture testbench of light52_tb is</beginfold id='5'>	60	<beginfold id='5'></beginfold id='5'>architecture testbench of light52_tb is
61		61
62	--------------------------------------------------------------------------------	62	--------------------------------------------------------------------------------
63	-- Simulation parameters	63	-- Simulation parameters
64	-- FIXME these should be in parameter package	64	-- FIXME these should be in parameter package
65		65
66	-- Simulated clock period is the same as the usual target, the DE-1 board	66	-- Simulated clock period is the same as the usual target, the DE-1 board
67	constant T : time := 20 ns<endfold id='18'>;</endfold id='18'> -- 50MHz	67	constant T : time := 20 ns<endfold id='18'></endfold id='18'>; -- 50MHz
68	constant SIMULATION_LENGTH : integer := 400000<endfold id='18'>;</endfold id='18'>	68	constant SIMULATION_LENGTH : integer := 400000<endfold id='18'></endfold id='18'>;
69		69
70	--------------------------------------------------------------------------------	70	--------------------------------------------------------------------------------
71	-- MPU interface	71	-- MPU interface
72		72
73	signal clk : std_logic := '0'<endfold id='18'>;</endfold id='18'>	73	signal clk : std_logic := '0'<endfold id='18'></endfold id='18'>;
74	signal reset : std_logic := '1'<endfold id='18'>;</endfold id='18'>	74	signal reset : std_logic := '1'<endfold id='18'></endfold id='18'>;
75		75
76	signal p0_out : std_logic_vector(7 downto 0)<endfold id='18'>;</endfold id='18'>	76	signal p0_out : std_logic_vector(7 downto 0)<endfold id='18'></endfold id='18'>;
77	signal p1_out : std_logic_vector(7 downto 0)<endfold id='18'>;</endfold id='18'>	77	signal p1_out : std_logic_vector(7 downto 0)<endfold id='18'></endfold id='18'>;
78	signal p2_in : std_logic_vector(7 downto 0)<endfold id='18'>;</endfold id='18'>	78	signal p2_in : std_logic_vector(7 downto 0)<endfold id='18'></endfold id='18'>;
79	signal p3_in : std_logic_vector(7 downto 0)<endfold id='18'>;</endfold id='18'>	79	signal p3_in : std_logic_vector(7 downto 0)<endfold id='18'></endfold id='18'>;
80		80
81	signal external_irq : std_logic_vector(7 downto 0)<endfold id='18'>;</endfold id='18'>	81	signal external_irq : std_logic_vector(7 downto 0)<endfold id='18'></endfold id='18'>;
82		82
83	signal txd, rxd : std_logic<endfold id='18'>;</endfold id='18'>	83	signal txd, rxd : std_logic<endfold id='18'></endfold id='18'>;
84		84
85	--------------------------------------------------------------------------------	85	--------------------------------------------------------------------------------
86	-- Logging signals & simulation control	86	-- Logging signals & simulation control
87		87
88	-- Asserted high to disable the clock and terminate the simulation.	88	-- Asserted high to disable the clock and terminate the simulation.
89	signal done : std_logic := '0'<endfold id='18'>;</endfold id='18'>	89	signal done : std_logic := '0'<endfold id='18'></endfold id='18'>;
90		90
91	-- Log file	91	-- Log file
92	file log_file: TEXT open write_mode is "hw_sim_log.txt";	92	file log_file: TEXT open write_mode is "hw_sim_log.txt";
93	-- Console output log file	93	-- Console output log file
94	file con_file: TEXT open write_mode is "hw_sim_console_log.txt";	94	file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
95	-- Info record needed by the logging fuctions	95	-- Info record needed by the logging fuctions
96	signal log_info : t_log_info<endfold id='18'>;</endfold id='18'>	96	signal log_info : t_log_info<endfold id='18'></endfold id='18'>;
97		97
98	begin	98	begin
99		99
100	---- UUT instantiation ---------------------------------------------------------	100	---- UUT instantiation ---------------------------------------------------------
101		101
102	<beginfold id='7'>uut: entity work.light52_mcu</beginfold id='7'>	102	<beginfold id='7'></beginfold id='7'>uut: entity work.light52_mcu
103	<beginfold id='10'>generic map (</beginfold id='10'>	103	<beginfold id='10'>generic map (</beginfold id='10'>
104	IMPLEMENT_BCD_INSTRUCTIONS => BCD,	104	IMPLEMENT_BCD_INSTRUCTIONS => BCD,
105	CODE_ROM_SIZE => work.obj_code_pkg.XCODE_SIZE,	105	CODE_ROM_SIZE => work.obj_code_pkg.XCODE_SIZE,
106	XDATA_RAM_SIZE => work.obj_code_pkg.XDATA_SIZE,	106	XDATA_RAM_SIZE => work.obj_code_pkg.XDATA_SIZE,
107	OBJ_CODE => work.obj_code_pkg.object_code	107	OBJ_CODE => work.obj_code_pkg.object_code
108	<endfold id='10'>)</endfold id='10'>	108	<endfold id='10'>)</endfold id='10'>
109	<beginfold id='10'>port map (</beginfold id='10'>	109	<beginfold id='10'>port map (</beginfold id='10'>
110	clk => clk,	110	clk => clk,
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