Differential D18516 Diff 50718 autotests/folding/light52_muldiv.vhdl.fold

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autotests/folding/light52_muldiv.vhdl.fold

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Line(s)		88	port(
99	div_ov_out : out std_logic;	99		div_ov_out : out std_logic;
100	mul_ov_out : out std_logic;	100		mul_ov_out : out std_logic;
101		101
102	mul_ready : out std_logic;	102		mul_ready : out std_logic;
103	div_ready : out std_logic	103		div_ready : out std_logic
104	);	104		);
105	<endfold id='16'>end entity light52_muldiv;</endfold id='16'>	105		<endfold id='16'>end entity light52_muldiv;</endfold id='16'>
106		106
107	<beginfold id='5'>architecture sequential of light52_muldiv is</beginfold id='5'>	107		<beginfold id='5'></beginfold id='5'>architecture sequential of light52_muldiv is
108		108
109	signal bit_ctr : integer range 0 to 8<endfold id='18'>;</endfold id='18'>	109		signal bit_ctr : integer range 0 to 8<endfold id='18'></endfold id='18'>;
110		110
111	signal b_shift_reg : t_word<endfold id='18'>;</endfold id='18'>	111		signal b_shift_reg : t_word<endfold id='18'></endfold id='18'>;
112		112
113	signal den_ge_256 : std_logic<endfold id='18'>;</endfold id='18'>	113		signal den_ge_256 : std_logic<endfold id='18'></endfold id='18'>;
114	signal num_ge_den : std_logic<endfold id='18'>;</endfold id='18'>	114		signal num_ge_den : std_logic<endfold id='18'></endfold id='18'>;
115	signal sub_num : std_logic<endfold id='18'>;</endfold id='18'>	115		signal sub_num : std_logic<endfold id='18'></endfold id='18'>;
116		116
117	signal denominator : t_byte<endfold id='18'>;</endfold id='18'>	117		signal denominator : t_byte<endfold id='18'></endfold id='18'>;
118	signal rem_reg : t_byte<endfold id='18'>;</endfold id='18'>	118		signal rem_reg : t_byte<endfold id='18'></endfold id='18'>;
119	signal quot_reg : t_byte<endfold id='18'>;</endfold id='18'>	119		signal quot_reg : t_byte<endfold id='18'></endfold id='18'>;
120	signal prod_reg : t_word<endfold id='18'>;</endfold id='18'>	120		signal prod_reg : t_word<endfold id='18'></endfold id='18'>;
121	signal ready : std_logic<endfold id='18'>;</endfold id='18'>	121		signal ready : std_logic<endfold id='18'></endfold id='18'>;
122		122
123	signal load_regs : std_logic<endfold id='18'>;</endfold id='18'>	123		signal load_regs : std_logic<endfold id='18'></endfold id='18'>;
124		124
125	begin	125		begin
126		126
127	-- Control logic ---------------------------------------------------------------	127		-- Control logic ---------------------------------------------------------------
128		128
129	control_counter: <beginfold id='9'>process</beginfold id='9'>(clk)	129		control_counter: <beginfold id='9'>process</beginfold id='9'>(clk)
130	begin	130		begin
131	if clk'event and clk='1' <beginfold id='13'>then</beginfold id='13'>	131		if clk'event and clk='1' <beginfold id='13'>then</beginfold id='13'>
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