-spawn(f) #=> #PID<0.40.0>
-
-# `spawn` returns a pid (process identifier), you can use this pid to send
-# messages to the process. To do message passing we use the `send` operator.
-# For all of this to be useful we need to be able to receive messages. This is
-# achieved with the `receive` mechanism:
-
-# The `receive do` block is used to listen for messages and process
-# them when they are received. A `receive do` block will only
-# process one received message. In order to process multiple
-# messages, a function with a `receive do` block must recursively
-# call itself to get into the `receive do` block again.
-
-defmodule Geometry do
- def area_loop do
- receive do
- {:rectangle, w, h} ->
- IO.puts("Area = #{w * h}")
- area_loop()
- {:circle, r} ->
- IO.puts("Area = #{3.14 * r * r}")
- area_loop()
- end
- end
-end
-
-# Compile the module and create a process that evaluates `area_loop` in the shell
-pid = spawn(fn -> Geometry.area_loop() end) #=> #PID<0.40.0>
-# Alternatively
-pid = spawn(Geometry, :area_loop, [])
-
-# Send a message to `pid` that will match a pattern in the receive statement
-send pid, {:rectangle, 2, 3}
-#=> Area = 6
-# {:rectangle,2,3}
-
-send pid, {:circle, 2}
-#=> Area = 12.56000000000000049738
-# {:circle,2}
-
-# The shell is also a process, you can use `self` to get the current pid
-self() #=> #PID<0.27.0>
diff --git a/autotests/input/syntax/elixir/results/hello.exs.reference.html b/autotests/input/syntax/elixir/results/hello.exs.reference.html
deleted file mode 100644
index ddab4c03..00000000
--- a/autotests/input/syntax/elixir/results/hello.exs.reference.html
+++ /dev/null
@@ -1,25 +0,0 @@
-
-
-
-
-
-
-hello.exs
-
-
-
-
-parent = self()
-
-# Spawns an Elixir process (not an operating system one!)
-spawn_link(fn ->
- send parent, {:msg, "hello world"}
-end)
-
-# Block until the message is received
-receive do
- {:msg, contents} -> IO.puts contents
-end
-
-
-
diff --git a/autotests/input/syntax/elixir/results/learnelixir.exs.reference.html b/autotests/input/syntax/elixir/results/learnelixir.exs.reference.html
deleted file mode 100644
index 97e3ccec..00000000
--- a/autotests/input/syntax/elixir/results/learnelixir.exs.reference.html
+++ /dev/null
@@ -1,411 +0,0 @@
-
-
-
-
-
-
-learnelixir.exs
-
-
-
-
-# Original: https://learnxinyminutes.com/docs/elixir/
-
-# Single line comments start with a number symbol.
-
-# There's no multi-line comment,
-# but you can stack multiple comments.
-
-# To use the elixir shell use the `iex` command.
-# Compile your modules with the `elixirc` command.
-
-# Both should be in your path if you installed elixir correctly.
-
-## ---------------------------
-## -- Basic types
-## ---------------------------
-
-# There are numbers
-3 # integer
-0x1F # integer
-3.0 # float
-
-# Atoms, that are literals, a constant with name. They start with `:`.
-:hello # atom
-
-# Tuples that are stored contiguously in memory.
-{1,2,3} # tuple
-
-# We can access a tuple element with the `elem` function:
-elem({1, 2, 3}, 0) #=> 1
-
-# Lists that are implemented as linked lists.
-[1,2,3] # list
-
-# We can access the head and tail of a list as follows:
-[head | tail] = [1,2,3]
-head #=> 1
-tail #=> [2,3]
-
-# In elixir, just like in Erlang, the `=` denotes pattern matching and
-# not an assignment.
-#
-# This means that the left-hand side (pattern) is matched against a
-# right-hand side.
-#
-# This is how the above example of accessing the head and tail of a list works.
-
-# A pattern match will error when the sides don't match, in this example
-# the tuples have different sizes.
-# {a, b, c} = {1, 2} #=> ** (MatchError) no match of right hand side value: {1,2}
-
-# There are also binaries
-<<1,2,3>> # binary
-
-# Strings and char lists
-"hello" # string
-'hello' # char list
-
-# Multi-line strings
-"""
-I'm a multi-line
-string.
-"""
-#=> "I'm a multi-line\nstring.\n"
-
-# Strings are all encoded in UTF-8:
-"héllò" #=> "héllò"
-
-# Strings are really just binaries, and char lists are just lists.
-<<?a, ?b, ?c>> #=> "abc"
-[?a, ?b, ?c] #=> 'abc'
-
-# `?a` in elixir returns the ASCII integer for the letter `a`
-?a #=> 97
-
-# To concatenate lists use `++`, for binaries use `<>`
-[1,2,3] ++ [4,5] #=> [1,2,3,4,5]
-'hello ' ++ 'world' #=> 'hello world'
-
-<<1,2,3>> <> <<4,5>> #=> <<1,2,3,4,5>>
-"hello " <> "world" #=> "hello world"
-
-# Ranges are represented as `start..end` (both inclusive)
-1..10 #=> 1..10
-lower..upper = 1..10 # Can use pattern matching on ranges as well
-[lower, upper] #=> [1, 10]
-
-## ---------------------------
-## -- Operators
-## ---------------------------
-
-# Some math
-1 + 1 #=> 2
-10 - 5 #=> 5
-5 * 2 #=> 10
-10 / 2 #=> 5.0
-
-# In elixir the operator `/` always returns a float.
-
-# To do integer division use `div`
-div(10, 2) #=> 5
-
-# To get the division remainder use `rem`
-rem(10, 3) #=> 1
-
-# There are also boolean operators: `or`, `and` and `not`.
-# These operators expect a boolean as their first argument.
-true and true #=> true
-false or true #=> true
-# 1 and true #=> ** (ArgumentError) argument error
-
-# Elixir also provides `||`, `&&` and `!` which accept arguments of any type.
-# All values except `false` and `nil` will evaluate to true.
-1 || true #=> 1
-false && 1 #=> false
-nil && 20 #=> nil
-!true #=> false
-
-# For comparisons we have: `==`, `!=`, `===`, `!==`, `<=`, `>=`, `<` and `>`
-1 == 1 #=> true
-1 != 1 #=> false
-1 < 2 #=> true
-
-# `===` and `!==` are more strict when comparing integers and floats:
-1 == 1.0 #=> true
-1 === 1.0 #=> false
-
-# We can also compare two different data types:
-1 < :hello #=> true
-
-# The overall sorting order is defined below:
-# number < atom < reference < functions < port < pid < tuple < list < bit string
-
-# To quote Joe Armstrong on this: "The actual order is not important,
-# but that a total ordering is well defined is important."
-
-## ---------------------------
-## -- Control Flow
-## ---------------------------
-
-# `if` expression
-if false do
- "This will never be seen"
-else
- "This will"
-end
-
-# There's also `unless`
-unless true do
- "This will never be seen"
-else
- "This will"
-end
-
-# Remember pattern matching? Many control-flow structures in elixir rely on it.
-
-# `case` allows us to compare a value against many patterns:
-case {:one, :two} do
- {:four, :five} ->
- "This won't match"
- {:one, x} ->
- "This will match and bind `x` to `:two`"
- _ ->
- "This will match any value"
-end
-
-# It's common to bind the value to `_` if we don't need it.
-# For example, if only the head of a list matters to us:
-[head | _] = [1,2,3]
-head #=> 1
-
-# For better readability we can do the following:
-[head | _tail] = [:a, :b, :c]
-head #=> :a
-
-# `cond` lets us check for many conditions at the same time.
-# Use `cond` instead of nesting many `if` expressions.
-cond do
- 1 + 1 == 3 ->
- "I will never be seen"
- 2 * 5 == 12 ->
- "Me neither"
- 1 + 2 == 3 ->
- "But I will"
-end
-
-# It is common to set the last condition equal to `true`, which will always match.
-cond do
- 1 + 1 == 3 ->
- "I will never be seen"
- 2 * 5 == 12 ->
- "Me neither"
- true ->
- "But I will (this is essentially an else)"
-end
-
-# `try/catch` is used to catch values that are thrown, it also supports an
-# `after` clause that is invoked whether or not a value is caught.
-try do
- throw(:hello)
-catch
- message -> "Got #{message}."
-after
- IO.puts("I'm the after clause.")
-end
-#=> I'm the after clause
-# "Got :hello"
-
-## ---------------------------
-## -- Modules and Functions
-## ---------------------------
-
-# Anonymous functions (notice the dot)
-square = fn(x) -> x * x end
-square.(5) #=> 25
-
-# They also accept many clauses and guards.
-# Guards let you fine tune pattern matching,
-# they are indicated by the `when` keyword:
-f = fn
- x, y when x > 0 -> x + y
- x, y -> x * y
-end
-
-f.(1, 3) #=> 4
-f.(-1, 3) #=> -3
-
-# Elixir also provides many built-in functions.
-# These are available in the current scope.
-is_number(10) #=> true
-is_list("hello") #=> false
-elem({1,2,3}, 0) #=> 1
-
-# You can group several functions into a module. Inside a module use `def`
-# to define your functions.
-defmodule Math do
- def sum(a, b) do
- a + b
- end
-
- def square(x) do
- x * x
- end
-end
-
-Math.sum(1, 2) #=> 3
-Math.square(3) #=> 9
-
-# To compile our simple Math module save it as `math.ex` and use `elixirc`
-# in your terminal: elixirc math.ex
-
-# Inside a module we can define functions with `def` and private functions with `defp`.
-# A function defined with `def` is available to be invoked from other modules,
-# a private function can only be invoked locally.
-defmodule PrivateMath do
- def sum(a, b) do
- do_sum(a, b)
- end
-
- defp do_sum(a, b) do
- a + b
- end
-end
-
-PrivateMath.sum(1, 2) #=> 3
-# PrivateMath.do_sum(1, 2) #=> ** (UndefinedFunctionError)
-
-# Function declarations also support guards and multiple clauses:
-defmodule Geometry do
- def area({:rectangle, w, h}) do
- w * h
- end
-
- def area({:circle, r}) when is_number(r) do
- 3.14 * r * r
- end
-end
-
-Geometry.area({:rectangle, 2, 3}) #=> 6
-Geometry.area({:circle, 3}) #=> 28.25999999999999801048
-# Geometry.area({:circle, "not_a_number"})
-#=> ** (FunctionClauseError) no function clause matching in Geometry.area/1
-
-# Due to immutability, recursion is a big part of elixir
-defmodule Recursion do
- def sum_list([head | tail], acc) do
- sum_list(tail, acc + head)
- end
-
- def sum_list([], acc) do
- acc
- end
-end
-
-Recursion.sum_list([1,2,3], 0) #=> 6
-
-# Elixir modules support attributes, there are built-in attributes and you
-# may also add custom ones.
-defmodule MyMod do
- @moduledoc """
- This is a built-in attribute on a example module.
- """
-
- @my_data 100 # This is a custom attribute.
- IO.inspect(@my_data) #=> 100
-end
-
-## ---------------------------
-## -- Structs and Exceptions
-## ---------------------------
-
-# Structs are extensions on top of maps that bring default values,
-# compile-time guarantees and polymorphism into Elixir.
-defmodule Person do
- defstruct name: nil, age: 0, height: 0
-end
-
-joe_info = %Person{ name: "Joe", age: 30, height: 180 }
-#=> %Person{age: 30, height: 180, name: "Joe"}
-
-# Access the value of name
-joe_info.name #=> "Joe"
-
-# Update the value of age
-older_joe_info = %{ joe_info | age: 31 }
-#=> %Person{age: 31, height: 180, name: "Joe"}
-
-# The `try` block with the `rescue` keyword is used to handle exceptions
-try do
- raise "some error"
-rescue
- RuntimeError -> "rescued a runtime error"
- _error -> "this will rescue any error"
-end
-#=> "rescued a runtime error"
-
-# All exceptions have a message
-try do
- raise "some error"
-rescue
- x in [RuntimeError] ->
- x.message
-end
-#=> "some error"
-
-## ---------------------------
-## -- Concurrency
-## ---------------------------
-
-# Elixir relies on the actor model for concurrency. All we need to write
-# concurrent programs in elixir are three primitives: spawning processes,
-# sending messages and receiving messages.
-
-# To start a new process we use the `spawn` function, which takes a function
-# as argument.
-f = fn -> 2 * 2 end #=> #Function<erl_eval.20.80484245>
-spawn(f) #=> #PID<0.40.0>
-
-# `spawn` returns a pid (process identifier), you can use this pid to send
-# messages to the process. To do message passing we use the `send` operator.
-# For all of this to be useful we need to be able to receive messages. This is
-# achieved with the `receive` mechanism:
-
-# The `receive do` block is used to listen for messages and process
-# them when they are received. A `receive do` block will only
-# process one received message. In order to process multiple
-# messages, a function with a `receive do` block must recursively
-# call itself to get into the `receive do` block again.
-
-defmodule Geometry do
- def area_loop do
- receive do
- {:rectangle, w, h} ->
- IO.puts("Area = #{w * h}")
- area_loop()
- {:circle, r} ->
- IO.puts("Area = #{3.14 * r * r}")
- area_loop()
- end
- end
-end
-
-# Compile the module and create a process that evaluates `area_loop` in the shell
-pid = spawn(fn -> Geometry.area_loop() end) #=> #PID<0.40.0>
-# Alternatively
-pid = spawn(Geometry, :area_loop, [])
-
-# Send a message to `pid` that will match a pattern in the receive statement
-send pid, {:rectangle, 2, 3}
-#=> Area = 6
-# {:rectangle,2,3}
-
-send pid, {:circle, 2}
-#=> Area = 12.56000000000000049738
-# {:circle,2}
-
-# The shell is also a process, you can use `self` to get the current pid
-self() #=> #PID<0.27.0>
-
-
-
diff --git a/autotests/input/syntax/j/results/test.ijs.reference.html b/autotests/input/syntax/j/results/test.ijs.reference.html
deleted file mode 100644
index c766d44b..00000000
--- a/autotests/input/syntax/j/results/test.ijs.reference.html
+++ /dev/null
@@ -1,75 +0,0 @@
-
-
-
-
-
-
-test.ijs
-
-
-
-
-Comment
-NB. This is a single line comment, check regions overlapping priority: 1 2.3 +/ &. 'quoted text'
-NB.(
-NB. This is a foldable multi line comment
-NB.)
-
-String literal
-''
-''''
-'This is quoted text'
-'And this '' and this NB. and this' 'Yet another quoted text'
-
-Numeric literal
-12 34.56 _7.89 1e2 1.2e3 _. _ __ 123j_456 2b111.111 1r23 123456x 1.2e3j4.5e6 _j_ __j_ _.j_. _j3p4j_.
-
-Parenthesis
-( )
-
-Adverb
-~ / \ /. \. } b. f. M. t. t:
-
-Conjuction
-^: . .. .: : :. :: ;. !. !: " ` `: @ @. @: & &. &: &.: d. D. D: H. L: S: T.
-
-Control
-assert. break. case. catch. catchd. catcht. continue. do. else. elseif. end. fcase. for. for_abc. goto_abc. if. label_abc. return. select. throw. try. while. whilst.
-
-Copula
-a =: 123
-(a) =: 123
-(a;b;c) =: 123
-'a b c' =: 123
-'a b c' =. '123'
-'`a b c' =. '123'
-'a' =: 123
-('a';'b';'c') =: 123
-
-Explicit argument
-x y m n u v x. y. m. n. u. v.
-
-Noun
-a. a:
-
-Verb
-= < <. <: > >. >: _: + +. +: * *. *: - -. -: % %. %: ^ ^. $ $. $: ~. ~: | |. |: , ,. ,: ; ;: # #. #: ! /: \: [ [: ] { {. {: {:: }. }: ". ": ? ?. A. C. e. E. i. i: I. j. L. o. p. p.. p: q: r. s: u: x: _9: _8: _7: _6: _5: _4: _3: _2: _1: 0: 1: 2: 3: 4: 5: 6: 7: 8: 9:
-
-Combined
-for_abc. i. 5 do. 55 return. end.
-a=. b =: 123 +/ # i. 10
-123 'qwerty'
-a_b =: '123' [ c__d =. 4 : 0 NB. foldable definition begins
- x +/ y
-)
-e__12 =: define NB. foldable definition begins
- if. x do. NB. inner foldable region begins
- y=. y + x NB. comment after code
- x +/ y
- else. NB. inner foldable region begins
- y +/ y
- end.
-)
-
-
-
diff --git a/autotests/input/syntax/j/test.ijs b/autotests/input/syntax/j/test.ijs
deleted file mode 100644
index 9acfe4b6..00000000
--- a/autotests/input/syntax/j/test.ijs
+++ /dev/null
@@ -1,61 +0,0 @@
-Comment
-NB. This is a single line comment, check regions overlapping priority: 1 2.3 +/ &. 'quoted text'
-NB.(
-NB. This is a foldable multi line comment
-NB.)
-
-String literal
-''
-''''
-'This is quoted text'
-'And this '' and this NB. and this' 'Yet another quoted text'
-
-Numeric literal
-12 34.56 _7.89 1e2 1.2e3 _. _ __ 123j_456 2b111.111 1r23 123456x 1.2e3j4.5e6 _j_ __j_ _.j_. _j3p4j_.
-
-Parenthesis
-( )
-
-Adverb
-~ / \ /. \. } b. f. M. t. t:
-
-Conjuction
-^: . .. .: : :. :: ;. !. !: " ` `: @ @. @: & &. &: &.: d. D. D: H. L: S: T.
-
-Control
-assert. break. case. catch. catchd. catcht. continue. do. else. elseif. end. fcase. for. for_abc. goto_abc. if. label_abc. return. select. throw. try. while. whilst.
-
-Copula
-a =: 123
-(a) =: 123
-(a;b;c) =: 123
-'a b c' =: 123
-'a b c' =. '123'
-'`a b c' =. '123'
-'a' =: 123
-('a';'b';'c') =: 123
-
-Explicit argument
-x y m n u v x. y. m. n. u. v.
-
-Noun
-a. a:
-
-Verb
-= < <. <: > >. >: _: + +. +: * *. *: - -. -: % %. %: ^ ^. $ $. $: ~. ~: | |. |: , ,. ,: ; ;: # #. #: ! /: \: [ [: ] { {. {: {:: }. }: ". ": ? ?. A. C. e. E. i. i: I. j. L. o. p. p.. p: q: r. s: u: x: _9: _8: _7: _6: _5: _4: _3: _2: _1: 0: 1: 2: 3: 4: 5: 6: 7: 8: 9:
-
-Combined
-for_abc. i. 5 do. 55 return. end.
-a=. b =: 123 +/ # i. 10
-123 'qwerty'
-a_b =: '123' [ c__d =. 4 : 0 NB. foldable definition begins
- x +/ y
-)
-e__12 =: define NB. foldable definition begins
- if. x do. NB. inner foldable region begins
- y=. y + x NB. comment after code
- x +/ y
- else. NB. inner foldable region begins
- y +/ y
- end.
-)
diff --git a/autotests/input/syntax/meson/meson.build b/autotests/input/syntax/meson/meson.build
deleted file mode 100644
index d6dd6e6b..00000000
--- a/autotests/input/syntax/meson/meson.build
+++ /dev/null
@@ -1,21 +0,0 @@
-# Unit test for Meson syntax highlight. License: LGPL
-project('projectname', 'cpp')
-
-
-
-sourcefiles = ['a.cpp', 'b.cpp']
-
-foreach sourcefile : sourcefiles
- message('this is a source file: ' + sourcefile)
-endforeach
-
-x=1
-if x+1 == 2 and x-1 == 0
- message('I can work in this universe!')
-endif
-
-subprojectresult = subproject('mysubprojectdir')
-
-mysharedlib = shared_library('libraryname', sourcefiles, linkwith: subprojectresult.staticlib)
-
-executable('myprogram', ['test.cpp'], linkwith: mysharedlib)
diff --git a/autotests/input/syntax/meson/results/meson.build.reference.html b/autotests/input/syntax/meson/results/meson.build.reference.html
deleted file mode 100644
index b79afe26..00000000
--- a/autotests/input/syntax/meson/results/meson.build.reference.html
+++ /dev/null
@@ -1,35 +0,0 @@
-
-
-
-
-
-
-meson.build
-
-
-
-
-# Unit test for Meson syntax highlight. License: LGPL
-project('projectname', 'cpp')
-
-
-
-sourcefiles = ['a.cpp', 'b.cpp']
-
-foreach sourcefile : sourcefiles
- message('this is a source file: ' + sourcefile)
-endforeach
-
-x=1
-if x+1 == 2 and x-1 == 0
- message('I can work in this universe!')
-endif
-
-subprojectresult = subproject('mysubprojectdir')
-
-mysharedlib = shared_library('libraryname', sourcefiles, linkwith: subprojectresult.staticlib)
-
-executable('myprogram', ['test.cpp'], linkwith: mysharedlib)
-
-
-
diff --git a/autotests/input/syntax/rmarkdown/example.rmd b/autotests/input/syntax/rmarkdown/example.rmd
deleted file mode 100644
index ef9a33e8..00000000
--- a/autotests/input/syntax/rmarkdown/example.rmd
+++ /dev/null
@@ -1,39 +0,0 @@
----
-title: "test"
-author: "me"
-date: "07.10.2014"
-output: html_document
----
-
-This is a simple test document. It shows syntax highlighting switches between YAML (above), R blocks
-```{r, echo=FALSE}
-for (i in 1:10) {
- if(i>=10) print(i)
-}
-# two blank lines below
-
-sessionInfo()
-```
-
-LaTeX equations,
-$$
-h_{i}(t \mid q,C) = h_{0}(t) e^{\beta_{1}quality_{i} + \beta_{2}C_{iq}}
-$$
-
-and Markdown. A [link](http://example.com) in Markdown.
-
-Inline `r y <- 5 + x - sin(3)` R code.
-Inline `y <- 5 + x - sin(3)` code.
-
-
- Heading
- =======
-
- Sub-heading
- -----------
- A list of editors:
- * kate
- * vim
- * emacs
-
-*italic*, **bold**, `monospace`
diff --git a/autotests/input/syntax/rmarkdown/results/example.rmd.reference.html b/autotests/input/syntax/rmarkdown/results/example.rmd.reference.html
deleted file mode 100644
index e1b8e564..00000000
--- a/autotests/input/syntax/rmarkdown/results/example.rmd.reference.html
+++ /dev/null
@@ -1,53 +0,0 @@
-
-
-
-
-
-
-example.rmd
-
-
-
-
----
-title: "test"
-author: "me"
-date: "07.10.2014"
-output: html_document
----
-
-This is a simple test document. It shows syntax highlighting switches between YAML (above), R blocks
-```{r, echo=FALSE}
-for (i in 1:10) {
- if(i>=10) print(i)
-}
-# two blank lines below
-
-sessionInfo()
-```
-
-LaTeX equations,
-$$
-h_{i}(t \mid q,C) = h_{0}(t) e^{\beta_{1}quality_{i} + \beta_{2}C_{iq}}
-$$
-
-and Markdown. A [link](http://example.com) in Markdown.
-
-Inline `r y <- 5 + x - sin(3)` R code.
-Inline `y <- 5 + x - sin(3)` code.
-
-
- Heading
- =======
-
- Sub-heading
- -----------
- A list of editors:
- * kate
- * vim
- * emacs
-
-*italic*, **bold**, `monospace`
-
-
-
diff --git a/autotests/input/syntax/sql-oracle/results/test_syntax.sql.reference.html b/autotests/input/syntax/sql-oracle/results/test_syntax.sql.reference.html
deleted file mode 100644
index d75a924c..00000000
--- a/autotests/input/syntax/sql-oracle/results/test_syntax.sql.reference.html
+++ /dev/null
@@ -1,54 +0,0 @@
-
-
-
-
-
-
-test_syntax.sql
-
-
-
-
--- kate: hl SQL (Oracle)
--- test case shipped with highlighting in bugzilla, LGPL
-
-begin
- q'{adfasdf'sadfasdf j}'{' hkjhkhkjhkjh khlkhklj'fghdfghdfgh'hkjh'jkhkh'a'
- Q'(asldflahsl;'dkjfhklsdfh)'
- q'[asdasd;'asdasd'a]sd'asd'asasd]';11111111[1']; asdasdasdasd'errrrrrrrrrrrrrr-p
-
- q'agdfgsdfgfhfghjfgh'f'f'sdfg'sdfg'dfg#a' dafdfadasfasdf;
-
- Q'#gdfgsdfgsdfgsdfgsdfg#' afgasasdfasdfasfasdfasdfasdfasdfsdf
-
- if sldfjsdj then
- case
- when 1=1 then
- aslfjsldkfj;
- when 2=2 then
- asdfg;
- else
- null;
- end case;
-
- if sdfjh then
- for i in 1 .. 2
- LOOP
- dbms_output.put_line(q';ololo;');
- END Loop;
-
- while true
- loop
- dbms_output.put_line('1111');
- end loop;
- end if;
- ksjfklasjd;
- fklj;
- elsif
- sdklfjsdklfj;
- else
- sdfdfsdf;
- end if;
-end;
-
-
diff --git a/autotests/input/syntax/sql-oracle/test_syntax.sql b/autotests/input/syntax/sql-oracle/test_syntax.sql
deleted file mode 100644
index a538349b..00000000
--- a/autotests/input/syntax/sql-oracle/test_syntax.sql
+++ /dev/null
@@ -1,41 +0,0 @@
--- kate: hl SQL (Oracle)
--- test case shipped with highlighting in bugzilla, LGPL
-
-begin
- q'{adfasdf'sadfasdf j}'{' hkjhkhkjhkjh khlkhklj'fghdfghdfgh'hkjh'jkhkh'a'
- Q'(asldflahsl;'dkjfhklsdfh)'
- q'[asdasd;'asdasd'a]sd'asd'asasd]';11111111[1']; asdasdasdasd'errrrrrrrrrrrrrr-p
-
- q'agdfgsdfgfhfghjfgh'f'f'sdfg'sdfg'dfg#a' dafdfadasfasdf;
-
- Q'#gdfgsdfgsdfgsdfgsdfg#' afgasasdfasdfasfasdfasdfasdfasdfsdf
-
- if sldfjsdj then
- case
- when 1=1 then
- aslfjsldkfj;
- when 2=2 then
- asdfg;
- else
- null;
- end case;
-
- if sdfjh then
- for i in 1 .. 2
- LOOP
- dbms_output.put_line(q';ololo;');
- END Loop;
-
- while true
- loop
- dbms_output.put_line('1111');
- end loop;
- end if;
- ksjfklasjd;
- fklj;
- elsif
- sdklfjsdklfj;
- else
- sdfdfsdf;
- end if;
-end;
\ No newline at end of file
diff --git a/autotests/input/syntax/verilog/or1200_dc_fsm.v b/autotests/input/syntax/verilog/or1200_dc_fsm.v
deleted file mode 100644
index e3d80ec9..00000000
--- a/autotests/input/syntax/verilog/or1200_dc_fsm.v
+++ /dev/null
@@ -1,563 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// OR1200's DC FSM ////
-//// ////
-//// This file is part of the OpenRISC 1200 project ////
-//// http://opencores.org/project,or1k ////
-//// ////
-//// Description ////
-//// Data cache state machine ////
-//// ////
-//// To Do: ////
-//// - Test error during line read or write ////
-//// ////
-//// Author(s): ////
-//// - Damjan Lampret, lampret@opencores.org ////
-//// - Julius Baxter, julius@opencores.org ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// $Log: or1200_dc_fsm.v,v $
-// Revision 2.0 2010/06/30 11:00:00 ORSoC
-// Minor update:
-// Bugs fixed.
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "or1200_defines.v"
-
-`define OR1200_DCFSM_IDLE 3'd0
-`define OR1200_DCFSM_CLOADSTORE 3'd1
-`define OR1200_DCFSM_LOOP2 3'd2
-`define OR1200_DCFSM_LOOP3 3'd3
-`define OR1200_DCFSM_LOOP4 3'd4
-`define OR1200_DCFSM_FLUSH5 3'd5
-`define OR1200_DCFSM_INV6 3'd6
-`define OR1200_DCFSM_WAITSPRCS7 3'd7
-
-
-
-//
-// Data cache FSM for cache line of 16 bytes (4x singleword)
-//
-
-module or1200_dc_fsm
- (
- // Clock and reset
- clk, rst,
-
- // Internal i/f to top level DC
- dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
- tagcomp_miss, biudata_valid, biudata_error, lsu_addr,
- dcram_we, biu_read, biu_write, biu_do_sel, dcram_di_sel, first_hit_ack,
- first_miss_ack, first_miss_err, burst, tag_we, tag_valid, dc_addr,
- dc_no_writethrough, tag_dirty, dirty, tag, tag_v, dc_block_flush,
- dc_block_writeback, spr_dat_i, mtspr_dc_done, spr_cswe
- );
-
- //
- // I/O
- //
- input clk;
- input rst;
- input dc_en;
- input dcqmem_cycstb_i;
- input dcqmem_ci_i;
- input dcqmem_we_i;
- input [3:0] dcqmem_sel_i;
- input tagcomp_miss;
- input biudata_valid;
- input biudata_error;
- input [31:0] lsu_addr;
- output [3:0] dcram_we;
- output biu_read;
- output biu_write;
- output dcram_di_sel;
- output biu_do_sel;
- output first_hit_ack;
- output first_miss_ack;
- output first_miss_err;
- output burst;
- output tag_we;
- output tag_valid;
- output [31:0] dc_addr;
- input dc_no_writethrough;
- output tag_dirty;
- input dirty;
- input [`OR1200_DCTAG_W-2:0] tag;
- input tag_v;
- input dc_block_flush;
- input dc_block_writeback;
- input [31:0] spr_dat_i;
- output mtspr_dc_done;
- input spr_cswe;
-
-
- //
- // Internal wires and regs
- //
- reg [31:0] addr_r;
- reg [2:0] state;
- reg [`OR1200_DCLS-1:0] cnt;
- reg hitmiss_eval;
- reg store;
- reg load;
- reg cache_inhibit;
- reg cache_miss;
- reg cache_dirty_needs_writeback;
- reg did_early_load_ack;
- reg cache_spr_block_flush;
- reg cache_spr_block_writeback;
- reg cache_wb;
- wire load_hit_ack;
- wire load_miss_ack;
- wire load_inhibit_ack;
- wire store_hit_ack;
- wire store_hit_writethrough_ack;
- wire store_miss_writethrough_ack;
- wire store_inhibit_ack;
- wire store_miss_ack;
- wire dcram_we_after_line_load;
- wire dcram_we_during_line_load;
- wire tagram_we_end_of_loadstore_loop;
- wire tagram_dirty_bit_set;
- wire writethrough;
- wire cache_inhibit_with_eval;
- wire [(`OR1200_DCLS-1)-2:0] next_addr_word;
-
- //
- // Cache inhibit
- //
-
- // Indicates whether cache is inhibited, during hitmiss_eval and after
- assign cache_inhibit_with_eval = (hitmiss_eval & dcqmem_ci_i) |
- (!hitmiss_eval & cache_inhibit);
-
- //
- // Generate of DCRAM write enables
- //
-
- // WE when non-writethrough, and had to wait for a line to load.
- assign dcram_we_after_line_load = (state == `OR1200_DCFSM_LOOP3) &
- dcqmem_we_i & !cache_dirty_needs_writeback &
- !did_early_load_ack;
-
- // WE when receiving the data cache line
- assign dcram_we_during_line_load = (state == `OR1200_DCFSM_LOOP2) & load &
- biudata_valid;
-
- assign dcram_we =(// Write when hit - make sure it is only when hit - could
- // maybe be doing write through and don't want to corrupt
- // cache lines corresponding to the writethrough addr_r.
- ({4{store_hit_ack | store_hit_writethrough_ack}} |
- // Write after load of line
- {4{dcram_we_after_line_load}}) &
- dcqmem_sel_i ) |
- // Write during load
- {4{dcram_we_during_line_load}};
-
- //
- // Tag RAM signals
- //
-
- // WE to tag RAM when we finish loading a line.
- assign tagram_we_end_of_loadstore_loop = ((state==`OR1200_DCFSM_LOOP2) &
- biudata_valid & !(|cnt));
-
-`ifndef OR1200_DC_WRITETHROUGH
- // No writethrough, so mark a line dirty whenever we write to it
- assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
-
- // Generate done signal for MTSPR instructions that may block execution
- assign mtspr_dc_done = // Either DC disabled or we're not selected, or
- !dc_en | !spr_cswe |
- // Requested address not valid or writeback and !dirty
- ((state==`OR1200_DCFSM_FLUSH5) &
- (!tag_v | (cache_spr_block_writeback & !dirty))) |
- // Writeback or flush is finished
- ((state==`OR1200_DCFSM_LOOP3) &
- (cache_spr_block_flush | cache_spr_block_writeback))|
- // Invalidate of clean line finished
- ((state==`OR1200_DCFSM_INV6) & cache_spr_block_flush);
-
-
-`else
- `ifdef OR1200_DC_NOSTACKWRITETHROUGH
- // For dirty bit setting when having writethrough but not for stack
- assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
- `else
- // Lines will never be dirty if always writethrough
- assign tagram_dirty_bit_set = 0;
- `endif
-
- assign mtspr_dc_done = 1'b1;
-
-`endif
-
- assign tag_dirty = tagram_dirty_bit_set;
-
- // WE to tag RAM
- assign tag_we = tagram_we_end_of_loadstore_loop |
- tagram_dirty_bit_set | (state == `OR1200_DCFSM_INV6);
-
-
- // Valid bit
- // Set valid when end of line load, or marking dirty (is still valid)
- assign tag_valid = ( tagram_we_end_of_loadstore_loop &
- (load | (store & cache_spr_block_writeback)) ) |
- tagram_dirty_bit_set;
-
-
-
- //
- // BIU read and write
- //
-
- assign biu_read = // Bus read request when:
- // 1) Have a miss and not dirty or a load with inhibit
- ((state == `OR1200_DCFSM_CLOADSTORE) &
- (((hitmiss_eval & tagcomp_miss & !dirty &
- !(store & writethrough)) |
- (load & cache_inhibit_with_eval)) & dcqmem_cycstb_i)) |
- // 2) In the loop and loading
- ((state == `OR1200_DCFSM_LOOP2) & load);
-
-
- assign biu_write = // Bus write request when:
- // 1) Have a miss and dirty or store with inhibit
- ((state == `OR1200_DCFSM_CLOADSTORE) &
- (((hitmiss_eval & tagcomp_miss & dirty) |
- (store & writethrough)) |
- (store & cache_inhibit_with_eval)) & dcqmem_cycstb_i) |
- // 2) In the loop and storing
- ((state == `OR1200_DCFSM_LOOP2) & store);
-
- //
- // Select for data to actual cache RAM (from LSU or BIU)
- //
- // Data to DCRAM - from external bus when loading (from IU when store)
- assign dcram_di_sel = load;
- // Data to external bus - always from IU except in case of bursting back
- // the line to memory. (1 selects DCRAM)
- assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;
-
- // 3-bit wire for calculating next word of burst write, depending on
- // line size of data cache.
- assign next_addr_word = addr_r[`OR1200_DCLS-1:2] + 1;
-
- // Address to cache RAM (tag address also derived from this)
- assign dc_addr =
- // First check if we've got a block flush or WB op
- ((dc_block_flush & !cache_spr_block_flush) |
- (dc_block_writeback & !cache_spr_block_writeback)) ?
- spr_dat_i :
- (state==`OR1200_DCFSM_FLUSH5) ? addr_r:
- // If no SPR action, then always put out address from LSU
- (state==`OR1200_DCFSM_IDLE | hitmiss_eval) ? lsu_addr :
- // Next, if in writeback loop, when ACKed must immediately
- // output next word address (the RAM address takes a cycle
- // to increment, but it's needed immediately for burst)
- // otherwise, output our registered address.
- (state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ?
- {addr_r[31:`OR1200_DCLS], next_addr_word, 2'b00} : addr_r;
-
-`ifdef OR1200_DC_WRITETHROUGH
- `ifdef OR1200_DC_NOSTACKWRITETHROUGH
- assign writethrough = !dc_no_writethrough;
- `else
- assign writethrough = 1;
- `endif
-`else
- assign writethrough = 0;
-`endif
-
- //
- // ACK generation for LSU
- //
-
- // ACK for when it's a cache hit
- assign first_hit_ack = load_hit_ack | store_hit_ack |
- store_hit_writethrough_ack |
- store_miss_writethrough_ack |
- store_inhibit_ack | store_miss_ack ;
-
- // ACK for when it's a cache miss - load only, is used in MUX for data back
- // LSU straight off external data bus. In
- // this was is also used for cache inhibit
- // loads.
- // first_hit_ack takes precedence over first_miss_ack
- assign first_miss_ack = ~first_hit_ack & (load_miss_ack | load_inhibit_ack);
-
- // ACK cache hit on load
- assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
-
- // ACK cache hit on store, no writethrough
- assign store_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
- store & !writethrough;
-
- // ACK cache hit on store with writethrough
- assign store_hit_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- !cache_miss & !cache_inhibit &
- store & writethrough & biudata_valid;
-
- // ACK cache miss on store with writethrough
- assign store_miss_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- cache_miss & !cache_inhibit &
- store & writethrough & biudata_valid;
-
- // ACK store when cacheinhibit
- assign store_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- store & cache_inhibit & biudata_valid;
-
-
- // Get the _early_ ack on first ACK back from wishbone during load only
- // Condition is that we're in the loop - that it's the first ack we get (can
- // tell from value of cnt), and we're loading a line to read from it (not
- // loading to write to it, in the case of a write without writethrough.)
- assign load_miss_ack = ((state== `OR1200_DCFSM_LOOP2) & load &
- (cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid &
- !(dcqmem_we_i & !writethrough));
-
- assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- load & cache_inhibit & biudata_valid;
-
- // This will be case of write through disabled, and had to load a line.
- assign store_miss_ack = dcram_we_after_line_load;
-
- assign first_miss_err = biudata_error & dcqmem_cycstb_i;
-
- // Signal burst when in the load/store loop. We will always try to burst.
- assign burst = (state == `OR1200_DCFSM_LOOP2);
-
- //
- // Main DC FSM
- //
- always @(posedge clk or `OR1200_RST_EVENT rst) begin
- if (rst == `OR1200_RST_VALUE) begin
- state <= `OR1200_DCFSM_IDLE;
- addr_r <= 32'd0;
- hitmiss_eval <= 1'b0;
- store <= 1'b0;
- load <= 1'b0;
- cnt <= `OR1200_DCLS'd0;
- cache_miss <= 1'b0;
- cache_dirty_needs_writeback <= 1'b0;
- cache_inhibit <= 1'b0;
- did_early_load_ack <= 1'b0;
- cache_spr_block_flush <= 1'b0;
- cache_spr_block_writeback <= 1'b0;
- end
- else
- case (state) // synopsys parallel_case
-
- `OR1200_DCFSM_IDLE : begin
- if (dc_en & (dc_block_flush | dc_block_writeback))
- begin
- cache_spr_block_flush <= dc_block_flush;
- cache_spr_block_writeback <= dc_block_writeback;
- hitmiss_eval <= 1'b1;
- state <= `OR1200_DCFSM_FLUSH5;
- addr_r <= spr_dat_i;
- end
- else if (dc_en & dcqmem_cycstb_i)
- begin
- state <= `OR1200_DCFSM_CLOADSTORE;
- hitmiss_eval <= 1'b1;
- store <= dcqmem_we_i;
- load <= !dcqmem_we_i;
- end
-
-
- end // case: `OR1200_DCFSM_IDLE
-
- `OR1200_DCFSM_CLOADSTORE: begin
- hitmiss_eval <= 1'b0;
- if (hitmiss_eval) begin
- cache_inhibit <= dcqmem_ci_i; // Check for cache inhibit here
- cache_miss <= tagcomp_miss;
- cache_dirty_needs_writeback <= dirty;
- addr_r <= lsu_addr;
- end
-
- // Evaluate any cache line load/stores in first cycle:
- //
- if (hitmiss_eval & tagcomp_miss & !(store & writethrough) &
- !dcqmem_ci_i)
- begin
- // Miss - first either:
- // 1) write back dirty line
- if (dirty) begin
- // Address for writeback
- addr_r <= {tag, lsu_addr[`OR1200_DCINDXH:2],2'd0};
- load <= 1'b0;
- store <= 1'b1;
-`ifdef OR1200_VERBOSE
- $display("%t: dcache miss and dirty", $time);
-`endif
- end
- // 2) load requested line
- else begin
- addr_r <= lsu_addr;
- load <= 1'b1;
- store <= 1'b0;
- end // else: !if(dirty)
- state <= `OR1200_DCFSM_LOOP2;
- // Set the counter for the burst accesses
- cnt <= ((1 << `OR1200_DCLS) - 4);
- end
- else if (// Strobe goes low
- !dcqmem_cycstb_i |
- // Cycle finishes
- (!hitmiss_eval & (biudata_valid | biudata_error)) |
- // Cache hit in first cycle....
- (hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
- // .. and you're not doing a writethrough store..
- !(store & writethrough))) begin
- state <= `OR1200_DCFSM_IDLE;
- load <= 1'b0;
- store <= 1'b0;
- cache_inhibit <= 1'b0;
- cache_dirty_needs_writeback <= 1'b0;
- end
- end // case: `OR1200_DCFSM_CLOADSTORE
-
- `OR1200_DCFSM_LOOP2 : begin // loop/abort
- if (!dc_en| biudata_error) begin
- state <= `OR1200_DCFSM_IDLE;
- load <= 1'b0;
- store <= 1'b0;
- cnt <= `OR1200_DCLS'd0;
- end
- if (biudata_valid & (|cnt)) begin
- cnt <= cnt - 4;
- addr_r[`OR1200_DCLS-1:2] <= addr_r[`OR1200_DCLS-1:2] + 1;
- end
- else if (biudata_valid & !(|cnt)) begin
- state <= `OR1200_DCFSM_LOOP3;
- addr_r <= lsu_addr;
- load <= 1'b0;
- store <= 1'b0;
- end
-
- // Track if we did an early ack during a load
- if (load_miss_ack)
- did_early_load_ack <= 1'b1;
-
-
- end // case: `OR1200_DCFSM_LOOP2
-
- `OR1200_DCFSM_LOOP3: begin // figure out next step
- if (cache_dirty_needs_writeback) begin
- // Just did store of the dirty line so now load new one
- load <= 1'b1;
- // Set the counter for the burst accesses
- cnt <= ((1 << `OR1200_DCLS) - 4);
- // Address of line to be loaded
- addr_r <= lsu_addr;
- cache_dirty_needs_writeback <= 1'b0;
- state <= `OR1200_DCFSM_LOOP2;
- end // if (cache_dirty_needs_writeback)
- else if (cache_spr_block_flush | cache_spr_block_writeback) begin
- // Just wrote back the line to memory, we're finished.
- cache_spr_block_flush <= 1'b0;
- cache_spr_block_writeback <= 1'b0;
- state <= `OR1200_DCFSM_WAITSPRCS7;
- end
- else begin
- // Just loaded a new line, finish up
- did_early_load_ack <= 1'b0;
- state <= `OR1200_DCFSM_LOOP4;
- end
- end // case: `OR1200_DCFSM_LOOP3
-
- `OR1200_DCFSM_LOOP4: begin
- state <= `OR1200_DCFSM_IDLE;
- end
-
- `OR1200_DCFSM_FLUSH5: begin
- hitmiss_eval <= 1'b0;
- if (hitmiss_eval & !tag_v)
- begin
- // Not even cached, just ignore
- cache_spr_block_flush <= 1'b0;
- cache_spr_block_writeback <= 1'b0;
- state <= `OR1200_DCFSM_WAITSPRCS7;
- end
- else if (hitmiss_eval & tag_v)
- begin
- // Tag is valid - what do we do?
- if ((cache_spr_block_flush | cache_spr_block_writeback) &
- dirty) begin
- // Need to writeback
- // Address for writeback (spr_dat_i has already changed so
- // use line number from addr_r)
- addr_r <= {tag, addr_r[`OR1200_DCINDXH:2],2'd0};
- load <= 1'b0;
- store <= 1'b1;
-`ifdef OR1200_VERBOSE
- $display("%t: block flush: dirty block", $time);
-`endif
- state <= `OR1200_DCFSM_LOOP2;
- // Set the counter for the burst accesses
- cnt <= ((1 << `OR1200_DCLS) - 4);
- end
- else if (cache_spr_block_flush & !dirty)
- begin
- // Line not dirty, just need to invalidate
- state <= `OR1200_DCFSM_INV6;
- end // else: !if(dirty)
- else if (cache_spr_block_writeback & !dirty)
- begin
- // Nothing to do - line is valid but not dirty
- cache_spr_block_writeback <= 1'b0;
- state <= `OR1200_DCFSM_WAITSPRCS7;
- end
- end // if (hitmiss_eval & tag_v)
- end
- `OR1200_DCFSM_INV6: begin
- cache_spr_block_flush <= 1'b0;
- // Wait until SPR CS goes low before going back to idle
- if (!spr_cswe)
- state <= `OR1200_DCFSM_IDLE;
- end
- `OR1200_DCFSM_WAITSPRCS7: begin
- // Wait until SPR CS goes low before going back to idle
- if (!spr_cswe)
- state <= `OR1200_DCFSM_IDLE;
- end
-
- endcase // case (state)
-
- end // always @ (posedge clk or `OR1200_RST_EVENT rst)
-
-
-endmodule
diff --git a/autotests/input/syntax/verilog/or1200_du.v b/autotests/input/syntax/verilog/or1200_du.v
deleted file mode 100644
index dbd36147..00000000
--- a/autotests/input/syntax/verilog/or1200_du.v
+++ /dev/null
@@ -1,1803 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// OR1200's Debug Unit ////
-//// ////
-//// This file is part of the OpenRISC 1200 project ////
-//// http://www.opencores.org/project,or1k ////
-//// ////
-//// Description ////
-//// Basic OR1200 debug unit. ////
-//// ////
-//// To Do: ////
-//// - make it smaller and faster ////
-//// ////
-//// Author(s): ////
-//// - Damjan Lampret, lampret@opencores.org ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-//
-// $Log: or1200_du.v,v $
-// Revision 2.0 2010/06/30 11:00:00 ORSoC
-// Minor update:
-// Bugs fixed.
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "or1200_defines.v"
-
-//
-// Debug unit
-//
-
-module or1200_du(
- // RISC Internal Interface
- clk, rst,
- dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
- dcpu_dat_dc, icpu_cycstb_i,
- ex_freeze, branch_op, ex_insn, id_pc,
- spr_dat_npc, rf_dataw,
- du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
- du_read, du_write, du_except_stop, du_hwbkpt, du_flush_pipe,
- spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
-
- // External Debug Interface
- dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
- dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
-);
-
-parameter dw = `OR1200_OPERAND_WIDTH;
-parameter aw = `OR1200_OPERAND_WIDTH;
-
-//
-// I/O
-//
-
-//
-// RISC Internal Interface
-//
-input clk; // Clock
-input rst; // Reset
-input dcpu_cycstb_i; // LSU status
-input dcpu_we_i; // LSU status
-input [31:0] dcpu_adr_i; // LSU addr
-input [31:0] dcpu_dat_lsu; // LSU store data
-input [31:0] dcpu_dat_dc; // LSU load data
-input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
-input ex_freeze; // EX stage freeze
-input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
-input [dw-1:0] ex_insn; // EX insn
-input [31:0] id_pc; // insn fetch EA
-input [31:0] spr_dat_npc; // Next PC (for trace)
-input [31:0] rf_dataw; // ALU result (for trace)
-output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
-output [24: 0] du_dmr1;
-output du_stall; // Debug Unit Stall
-output [aw-1:0] du_addr; // Debug Unit Address
-input [dw-1:0] du_dat_i; // Debug Unit Data In
-output [dw-1:0] du_dat_o; // Debug Unit Data Out
-output du_read; // Debug Unit Read Enable
-output du_write; // Debug Unit Write Enable
-input [13:0] du_except_stop; // Exception masked by DSR
-output du_hwbkpt; // Cause trap exception (HW Breakpoints)
-output du_flush_pipe; // Cause pipeline flush and pc<-npc
-input spr_cs; // SPR Chip Select
-input spr_write; // SPR Read/Write
-input [aw-1:0] spr_addr; // SPR Address
-input [dw-1:0] spr_dat_i; // SPR Data Input
-output [dw-1:0] spr_dat_o; // SPR Data Output
-
-//
-// External Debug Interface
-//
-input dbg_stall_i; // External Stall Input
-input dbg_ewt_i; // External Watchpoint Trigger Input
-output [3:0] dbg_lss_o; // External Load/Store Unit Status
-output [1:0] dbg_is_o; // External Insn Fetch Status
-output [10:0] dbg_wp_o; // Watchpoints Outputs
-output dbg_bp_o; // Breakpoint Output
-input dbg_stb_i; // External Address/Data Strobe
-input dbg_we_i; // External Write Enable
-input [aw-1:0] dbg_adr_i; // External Address Input
-input [dw-1:0] dbg_dat_i; // External Data Input
-output [dw-1:0] dbg_dat_o; // External Data Output
-output dbg_ack_o; // External Data Acknowledge (not WB compatible)
-reg [dw-1:0] dbg_dat_o; // External Data Output
-reg dbg_ack_o; // External Data Acknowledge (not WB compatible)
-
-
-//
-// Some connections go directly from the CPU through DU to Debug I/F
-//
-`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
-assign dbg_lss_o = 4'b0000;
-
-reg [1:0] dbg_is_o;
-//
-// Show insn activity (temp, must be removed)
-//
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dbg_is_o <= 2'b00;
- else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
- dbg_is_o <= ~dbg_is_o;
-`ifdef UNUSED
-assign dbg_is_o = 2'b00;
-`endif
-`else
-assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
-assign dbg_is_o = {1'b0, icpu_cycstb_i};
-`endif
-assign dbg_wp_o = 11'b000_0000_0000;
-
-//
-// Some connections go directly from Debug I/F through DU to the CPU
-//
-assign du_stall = dbg_stall_i;
-assign du_addr = dbg_adr_i;
-assign du_dat_o = dbg_dat_i;
-assign du_read = dbg_stb_i && !dbg_we_i;
-assign du_write = dbg_stb_i && dbg_we_i;
-
-//
-// After a sw breakpoint, the replaced instruction need to be executed.
-// We flush the entire pipeline and set the pc to the current address
-// to execute the restored address.
-//
-
-reg du_flush_pipe_r;
-reg dbg_stall_i_r;
-
-assign du_flush_pipe = du_flush_pipe_r;
-
-//
-// Register du_flush_pipe
-//
-always @(posedge clk or `OR1200_RST_EVENT rst) begin
- if (rst == `OR1200_RST_VALUE) begin
- du_flush_pipe_r <= 1'b0;
- end
- else begin
- du_flush_pipe_r <= (dbg_stall_i_r && !dbg_stall_i && |du_except_stop);
- end
-end
-
-//
-// Detect dbg_stall falling edge
-//
-always @(posedge clk or `OR1200_RST_EVENT rst) begin
- if (rst == `OR1200_RST_VALUE) begin
- dbg_stall_i_r <= 1'b0;
- end
- else begin
- dbg_stall_i_r <= dbg_stall_i;
- end
-end
-
-reg dbg_ack;
-//
-// Generate acknowledge -- just delay stb signal
-//
-always @(posedge clk or `OR1200_RST_EVENT rst) begin
- if (rst == `OR1200_RST_VALUE) begin
- dbg_ack <= 1'b0;
- dbg_ack_o <= 1'b0;
- end
- else begin
- dbg_ack <= dbg_stb_i; // valid when du_dat_i
- dbg_ack_o <= dbg_ack & dbg_stb_i; // valid when dbg_dat_o
- end
-end
-
-//
-// Register data output
-//
-always @(posedge clk)
- dbg_dat_o <= du_dat_i;
-
-`ifdef OR1200_DU_IMPLEMENTED
-
-//
-// Debug Mode Register 1
-//
-`ifdef OR1200_DU_DMR1
-reg [24:0] dmr1; // DMR1 implemented
-`else
-wire [24:0] dmr1; // DMR1 not implemented
-`endif
-assign du_dmr1 = dmr1;
-
-//
-// Debug Mode Register 2
-//
-`ifdef OR1200_DU_DMR2
-reg [23:0] dmr2; // DMR2 implemented
-`else
-wire [23:0] dmr2; // DMR2 not implemented
-`endif
-
-//
-// Debug Stop Register
-//
-`ifdef OR1200_DU_DSR
-reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
-`else
-wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
-`endif
-
-//
-// Debug Reason Register
-//
-`ifdef OR1200_DU_DRR
-reg [13:0] drr; // DRR implemented
-`else
-wire [13:0] drr; // DRR not implemented
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR0
-reg [31:0] dvr0;
-`else
-wire [31:0] dvr0;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR1
-reg [31:0] dvr1;
-`else
-wire [31:0] dvr1;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR2
-reg [31:0] dvr2;
-`else
-wire [31:0] dvr2;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR3
-reg [31:0] dvr3;
-`else
-wire [31:0] dvr3;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR4
-reg [31:0] dvr4;
-`else
-wire [31:0] dvr4;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR5
-reg [31:0] dvr5;
-`else
-wire [31:0] dvr5;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR6
-reg [31:0] dvr6;
-`else
-wire [31:0] dvr6;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR7
-reg [31:0] dvr7;
-`else
-wire [31:0] dvr7;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR0
-reg [7:0] dcr0;
-`else
-wire [7:0] dcr0;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR1
-reg [7:0] dcr1;
-`else
-wire [7:0] dcr1;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR2
-reg [7:0] dcr2;
-`else
-wire [7:0] dcr2;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR3
-reg [7:0] dcr3;
-`else
-wire [7:0] dcr3;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR4
-reg [7:0] dcr4;
-`else
-wire [7:0] dcr4;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR5
-reg [7:0] dcr5;
-`else
-wire [7:0] dcr5;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR6
-reg [7:0] dcr6;
-`else
-wire [7:0] dcr6;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR7
-reg [7:0] dcr7;
-`else
-wire [7:0] dcr7;
-`endif
-
-//
-// Debug Watchpoint Counter Register 0
-//
-`ifdef OR1200_DU_DWCR0
-reg [31:0] dwcr0;
-`else
-wire [31:0] dwcr0;
-`endif
-
-//
-// Debug Watchpoint Counter Register 1
-//
-`ifdef OR1200_DU_DWCR1
-reg [31:0] dwcr1;
-`else
-wire [31:0] dwcr1;
-`endif
-
-//
-// Internal wires
-//
-wire dmr1_sel; // DMR1 select
-wire dmr2_sel; // DMR2 select
-wire dsr_sel; // DSR select
-wire drr_sel; // DRR select
-wire dvr0_sel,
- dvr1_sel,
- dvr2_sel,
- dvr3_sel,
- dvr4_sel,
- dvr5_sel,
- dvr6_sel,
- dvr7_sel; // DVR selects
-wire dcr0_sel,
- dcr1_sel,
- dcr2_sel,
- dcr3_sel,
- dcr4_sel,
- dcr5_sel,
- dcr6_sel,
- dcr7_sel; // DCR selects
-wire dwcr0_sel,
- dwcr1_sel; // DWCR selects
-reg dbg_bp_r;
-reg ex_freeze_q;
-`ifdef OR1200_DU_HWBKPTS
-reg [31:0] match_cond0_ct;
-reg [31:0] match_cond1_ct;
-reg [31:0] match_cond2_ct;
-reg [31:0] match_cond3_ct;
-reg [31:0] match_cond4_ct;
-reg [31:0] match_cond5_ct;
-reg [31:0] match_cond6_ct;
-reg [31:0] match_cond7_ct;
-reg match_cond0_stb;
-reg match_cond1_stb;
-reg match_cond2_stb;
-reg match_cond3_stb;
-reg match_cond4_stb;
-reg match_cond5_stb;
-reg match_cond6_stb;
-reg match_cond7_stb;
-reg match0;
-reg match1;
-reg match2;
-reg match3;
-reg match4;
-reg match5;
-reg match6;
-reg match7;
-reg wpcntr0_match;
-reg wpcntr1_match;
-reg incr_wpcntr0;
-reg incr_wpcntr1;
-reg [10:0] wp;
-`endif
-wire du_hwbkpt;
-reg du_hwbkpt_hold;
-`ifdef OR1200_DU_READREGS
-reg [31:0] spr_dat_o;
-`endif
-reg [13:0] except_stop; // Exceptions that stop because of DSR
-`ifdef OR1200_DU_TB_IMPLEMENTED
-wire tb_enw;
-reg [7:0] tb_wadr;
-reg [31:0] tb_timstmp;
-`endif
-wire [31:0] tbia_dat_o;
-wire [31:0] tbim_dat_o;
-wire [31:0] tbar_dat_o;
-wire [31:0] tbts_dat_o;
-
-//
-// DU registers address decoder
-//
-`ifdef OR1200_DU_DMR1
-assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
-`endif
-`ifdef OR1200_DU_DMR2
-assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
-`endif
-`ifdef OR1200_DU_DSR
-assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
-`endif
-`ifdef OR1200_DU_DRR
-assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
-`endif
-`ifdef OR1200_DU_DVR0
-assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
-`endif
-`ifdef OR1200_DU_DVR1
-assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
-`endif
-`ifdef OR1200_DU_DVR2
-assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
-`endif
-`ifdef OR1200_DU_DVR3
-assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
-`endif
-`ifdef OR1200_DU_DVR4
-assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
-`endif
-`ifdef OR1200_DU_DVR5
-assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
-`endif
-`ifdef OR1200_DU_DVR6
-assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
-`endif
-`ifdef OR1200_DU_DVR7
-assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
-`endif
-`ifdef OR1200_DU_DCR0
-assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
-`endif
-`ifdef OR1200_DU_DCR1
-assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
-`endif
-`ifdef OR1200_DU_DCR2
-assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
-`endif
-`ifdef OR1200_DU_DCR3
-assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
-`endif
-`ifdef OR1200_DU_DCR4
-assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
-`endif
-`ifdef OR1200_DU_DCR5
-assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
-`endif
-`ifdef OR1200_DU_DCR6
-assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
-`endif
-`ifdef OR1200_DU_DCR7
-assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
-`endif
-`ifdef OR1200_DU_DWCR0
-assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
-`endif
-`ifdef OR1200_DU_DWCR1
-assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
-`endif
-
-// Track previous ex_freeze to detect when signals are updated
-always @(posedge clk)
- ex_freeze_q <= ex_freeze;
-
-//
-// Decode started exception
-//
-// du_except_stop comes from or1200_except
-//
-always @(du_except_stop or ex_freeze_q) begin
- except_stop = 14'b00_0000_0000_0000;
- casez (du_except_stop)
- 14'b1?_????_????_????:
- except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
- 14'b01_????_????_????: begin
- except_stop[`OR1200_DU_DRR_IE] = 1'b1;
- end
- 14'b00_1???_????_????: begin
- except_stop[`OR1200_DU_DRR_IME] = 1'b1;
- end
- 14'b00_01??_????_????:
- except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
- 14'b00_001?_????_????: begin
- except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
- end
- 14'b00_0001_????_????:
- except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
- 14'b00_0000_1???_????: begin
- except_stop[`OR1200_DU_DRR_AE] = 1'b1;
- end
- 14'b00_0000_01??_????: begin
- except_stop[`OR1200_DU_DRR_DME] = 1'b1;
- end
- 14'b00_0000_001?_????:
- except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
- 14'b00_0000_0001_????:
- except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
- 14'b00_0000_0000_1???: begin
- except_stop[`OR1200_DU_DRR_RE] = 1'b1;
- end
- 14'b00_0000_0000_01??: begin
- except_stop[`OR1200_DU_DRR_TE] = 1'b1 & ~ex_freeze_q;
- end
- 14'b00_0000_0000_001?: begin
- except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
- end
- 14'b00_0000_0000_0001:
- except_stop[`OR1200_DU_DRR_SCE] = 1'b1 & ~ex_freeze_q;
- default:
- except_stop = 14'b00_0000_0000_0000;
- endcase // casez (du_except_stop)
-end
-
-//
-// dbg_bp_o is registered
-//
-assign dbg_bp_o = dbg_bp_r;
-
-//
-// Breakpoint activation register
-//
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dbg_bp_r <= 1'b0;
- else if (!ex_freeze)
- dbg_bp_r <= |except_stop
-`ifdef OR1200_DU_DMR1_ST
- | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
-`endif
-`ifdef OR1200_DU_DMR1_BT
- | (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
-`endif
- ;
- else
- dbg_bp_r <= |except_stop;
-
-//
-// Write to DMR1
-//
-`ifdef OR1200_DU_DMR1
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dmr1 <= 25'h000_0000;
- else if (dmr1_sel && spr_write)
-`ifdef OR1200_DU_HWBKPTS
- dmr1 <= spr_dat_i[24:0];
-`else
- dmr1 <= {1'b0, spr_dat_i[23:22], 22'h00_0000};
-`endif
-`else
-assign dmr1 = 25'h000_0000;
-`endif
-
-//
-// Write to DMR2
-//
-`ifdef OR1200_DU_DMR2
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dmr2 <= 24'h00_0000;
- else if (dmr2_sel && spr_write)
- dmr2 <= spr_dat_i[23:0];
-`else
-assign dmr2 = 24'h00_0000;
-`endif
-
-//
-// Write to DSR
-//
-`ifdef OR1200_DU_DSR
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
- else if (dsr_sel && spr_write)
- dsr <= spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
-`else
-assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
-`endif
-
-//
-// Write to DRR
-//
-`ifdef OR1200_DU_DRR
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- drr <= 14'b0;
- else if (drr_sel && spr_write)
- drr <= spr_dat_i[13:0];
- else
- drr <= drr | except_stop;
-`else
-assign drr = 14'b0;
-`endif
-
-//
-// Write to DVR0
-//
-`ifdef OR1200_DU_DVR0
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr0 <= 32'h0000_0000;
- else if (dvr0_sel && spr_write)
- dvr0 <= spr_dat_i[31:0];
-`else
-assign dvr0 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR1
-//
-`ifdef OR1200_DU_DVR1
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr1 <= 32'h0000_0000;
- else if (dvr1_sel && spr_write)
- dvr1 <= spr_dat_i[31:0];
-`else
-assign dvr1 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR2
-//
-`ifdef OR1200_DU_DVR2
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr2 <= 32'h0000_0000;
- else if (dvr2_sel && spr_write)
- dvr2 <= spr_dat_i[31:0];
-`else
-assign dvr2 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR3
-//
-`ifdef OR1200_DU_DVR3
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr3 <= 32'h0000_0000;
- else if (dvr3_sel && spr_write)
- dvr3 <= spr_dat_i[31:0];
-`else
-assign dvr3 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR4
-//
-`ifdef OR1200_DU_DVR4
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr4 <= 32'h0000_0000;
- else if (dvr4_sel && spr_write)
- dvr4 <= spr_dat_i[31:0];
-`else
-assign dvr4 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR5
-//
-`ifdef OR1200_DU_DVR5
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr5 <= 32'h0000_0000;
- else if (dvr5_sel && spr_write)
- dvr5 <= spr_dat_i[31:0];
-`else
-assign dvr5 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR6
-//
-`ifdef OR1200_DU_DVR6
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr6 <= 32'h0000_0000;
- else if (dvr6_sel && spr_write)
- dvr6 <= spr_dat_i[31:0];
-`else
-assign dvr6 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR7
-//
-`ifdef OR1200_DU_DVR7
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr7 <= 32'h0000_0000;
- else if (dvr7_sel && spr_write)
- dvr7 <= spr_dat_i[31:0];
-`else
-assign dvr7 = 32'h0000_0000;
-`endif
-
-//
-// Write to DCR0
-//
-`ifdef OR1200_DU_DCR0
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr0 <= 8'h00;
- else if (dcr0_sel && spr_write)
- dcr0 <= spr_dat_i[7:0];
-`else
-assign dcr0 = 8'h00;
-`endif
-
-//
-// Write to DCR1
-//
-`ifdef OR1200_DU_DCR1
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr1 <= 8'h00;
- else if (dcr1_sel && spr_write)
- dcr1 <= spr_dat_i[7:0];
-`else
-assign dcr1 = 8'h00;
-`endif
-
-//
-// Write to DCR2
-//
-`ifdef OR1200_DU_DCR2
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr2 <= 8'h00;
- else if (dcr2_sel && spr_write)
- dcr2 <= spr_dat_i[7:0];
-`else
-assign dcr2 = 8'h00;
-`endif
-
-//
-// Write to DCR3
-//
-`ifdef OR1200_DU_DCR3
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr3 <= 8'h00;
- else if (dcr3_sel && spr_write)
- dcr3 <= spr_dat_i[7:0];
-`else
-assign dcr3 = 8'h00;
-`endif
-
-//
-// Write to DCR4
-//
-`ifdef OR1200_DU_DCR4
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr4 <= 8'h00;
- else if (dcr4_sel && spr_write)
- dcr4 <= spr_dat_i[7:0];
-`else
-assign dcr4 = 8'h00;
-`endif
-
-//
-// Write to DCR5
-//
-`ifdef OR1200_DU_DCR5
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr5 <= 8'h00;
- else if (dcr5_sel && spr_write)
- dcr5 <= spr_dat_i[7:0];
-`else
-assign dcr5 = 8'h00;
-`endif
-
-//
-// Write to DCR6
-//
-`ifdef OR1200_DU_DCR6
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr6 <= 8'h00;
- else if (dcr6_sel && spr_write)
- dcr6 <= spr_dat_i[7:0];
-`else
-assign dcr6 = 8'h00;
-`endif
-
-//
-// Write to DCR7
-//
-`ifdef OR1200_DU_DCR7
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr7 <= 8'h00;
- else if (dcr7_sel && spr_write)
- dcr7 <= spr_dat_i[7:0];
-`else
-assign dcr7 = 8'h00;
-`endif
-
-//
-// Write to DWCR0
-//
-`ifdef OR1200_DU_DWCR0
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dwcr0 <= 32'h0000_0000;
- else if (dwcr0_sel && spr_write)
- dwcr0 <= spr_dat_i[31:0];
- else if (incr_wpcntr0)
- dwcr0[`OR1200_DU_DWCR_COUNT] <= dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
-`else
-assign dwcr0 = 32'h0000_0000;
-`endif
-
-//
-// Write to DWCR1
-//
-`ifdef OR1200_DU_DWCR1
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dwcr1 <= 32'h0000_0000;
- else if (dwcr1_sel && spr_write)
- dwcr1 <= spr_dat_i[31:0];
- else if (incr_wpcntr1)
- dwcr1[`OR1200_DU_DWCR_COUNT] <= dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
-`else
-assign dwcr1 = 32'h0000_0000;
-`endif
-
-//
-// Read DU registers
-//
-`ifdef OR1200_DU_READREGS
-always @(spr_addr or dsr or drr or dmr1 or dmr2
- or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
- or dvr5 or dvr6 or dvr7
- or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
- or dcr5 or dcr6 or dcr7
- or dwcr0 or dwcr1
-`ifdef OR1200_DU_TB_IMPLEMENTED
- or tb_wadr or tbia_dat_o or tbim_dat_o
- or tbar_dat_o or tbts_dat_o
-`endif
- )
- casez (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
-`ifdef OR1200_DU_DVR0
- `OR1200_DU_DVR0:
- spr_dat_o = dvr0;
-`endif
-`ifdef OR1200_DU_DVR1
- `OR1200_DU_DVR1:
- spr_dat_o = dvr1;
-`endif
-`ifdef OR1200_DU_DVR2
- `OR1200_DU_DVR2:
- spr_dat_o = dvr2;
-`endif
-`ifdef OR1200_DU_DVR3
- `OR1200_DU_DVR3:
- spr_dat_o = dvr3;
-`endif
-`ifdef OR1200_DU_DVR4
- `OR1200_DU_DVR4:
- spr_dat_o = dvr4;
-`endif
-`ifdef OR1200_DU_DVR5
- `OR1200_DU_DVR5:
- spr_dat_o = dvr5;
-`endif
-`ifdef OR1200_DU_DVR6
- `OR1200_DU_DVR6:
- spr_dat_o = dvr6;
-`endif
-`ifdef OR1200_DU_DVR7
- `OR1200_DU_DVR7:
- spr_dat_o = dvr7;
-`endif
-`ifdef OR1200_DU_DCR0
- `OR1200_DU_DCR0:
- spr_dat_o = {24'h00_0000, dcr0};
-`endif
-`ifdef OR1200_DU_DCR1
- `OR1200_DU_DCR1:
- spr_dat_o = {24'h00_0000, dcr1};
-`endif
-`ifdef OR1200_DU_DCR2
- `OR1200_DU_DCR2:
- spr_dat_o = {24'h00_0000, dcr2};
-`endif
-`ifdef OR1200_DU_DCR3
- `OR1200_DU_DCR3:
- spr_dat_o = {24'h00_0000, dcr3};
-`endif
-`ifdef OR1200_DU_DCR4
- `OR1200_DU_DCR4:
- spr_dat_o = {24'h00_0000, dcr4};
-`endif
-`ifdef OR1200_DU_DCR5
- `OR1200_DU_DCR5:
- spr_dat_o = {24'h00_0000, dcr5};
-`endif
-`ifdef OR1200_DU_DCR6
- `OR1200_DU_DCR6:
- spr_dat_o = {24'h00_0000, dcr6};
-`endif
-`ifdef OR1200_DU_DCR7
- `OR1200_DU_DCR7:
- spr_dat_o = {24'h00_0000, dcr7};
-`endif
-`ifdef OR1200_DU_DMR1
- `OR1200_DU_DMR1:
- spr_dat_o = {7'h00, dmr1};
-`endif
-`ifdef OR1200_DU_DMR2
- `OR1200_DU_DMR2:
- spr_dat_o = {8'h00, dmr2};
-`endif
-`ifdef OR1200_DU_DWCR0
- `OR1200_DU_DWCR0:
- spr_dat_o = dwcr0;
-`endif
-`ifdef OR1200_DU_DWCR1
- `OR1200_DU_DWCR1:
- spr_dat_o = dwcr1;
-`endif
-`ifdef OR1200_DU_DSR
- `OR1200_DU_DSR:
- spr_dat_o = {18'b0, dsr};
-`endif
-`ifdef OR1200_DU_DRR
- `OR1200_DU_DRR:
- spr_dat_o = {18'b0, drr};
-`endif
-`ifdef OR1200_DU_TB_IMPLEMENTED
- `OR1200_DU_TBADR:
- spr_dat_o = {24'h000000, tb_wadr};
- `OR1200_DU_TBIA:
- spr_dat_o = tbia_dat_o;
- `OR1200_DU_TBIM:
- spr_dat_o = tbim_dat_o;
- `OR1200_DU_TBAR:
- spr_dat_o = tbar_dat_o;
- `OR1200_DU_TBTS:
- spr_dat_o = tbts_dat_o;
-`endif
- default:
- spr_dat_o = 32'h0000_0000;
- endcase
-`endif
-
-//
-// DSR alias
-//
-assign du_dsr = dsr;
-
-`ifdef OR1200_DU_HWBKPTS
-
-//
-// Compare To What (Match Condition 0)
-//
-always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond0_ct = id_pc; // insn fetch EA
- 3'b010: match_cond0_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond0_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond0_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond0_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond0_ct = dcpu_adr_i; // load/store EA
- default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 0)
-//
-always @(dcr0 or dcpu_cycstb_i)
- case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond0_stb = 1'b0; //comparison disabled
- 3'b001: match_cond0_stb = 1'b1; // insn fetch EA
- default:match_cond0_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 0
-//
-always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
- casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match0 = 1'b0;
- 4'b1_001: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} ==
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_010: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_011: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <=
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_100: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_101: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >=
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_110: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} !=
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- endcase
-
-//
-// Watchpoint 0
-//
-always @(dmr1 or match0)
- case (dmr1[`OR1200_DU_DMR1_CW0])
- 2'b00: wp[0] = match0;
- 2'b01: wp[0] = match0;
- 2'b10: wp[0] = match0;
- 2'b11: wp[0] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 1)
-//
-always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond1_ct = id_pc; // insn fetch EA
- 3'b010: match_cond1_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond1_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond1_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond1_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond1_ct = dcpu_adr_i; // load/store EA
- default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 1)
-//
-always @(dcr1 or dcpu_cycstb_i)
- case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond1_stb = 1'b0; //comparison disabled
- 3'b001: match_cond1_stb = 1'b1; // insn fetch EA
- default:match_cond1_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 1
-//
-always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
- casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match1 = 1'b0;
- 4'b1_001: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} ==
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_010: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_011: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <=
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_100: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_101: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >=
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_110: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} !=
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- endcase
-
-//
-// Watchpoint 1
-//
-always @(dmr1 or match1 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW1])
- 2'b00: wp[1] = match1;
- 2'b01: wp[1] = match1 & wp[0];
- 2'b10: wp[1] = match1 | wp[0];
- 2'b11: wp[1] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 2)
-//
-always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond2_ct = id_pc; // insn fetch EA
- 3'b010: match_cond2_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond2_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond2_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond2_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond2_ct = dcpu_adr_i; // load/store EA
- default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 2)
-//
-always @(dcr2 or dcpu_cycstb_i)
- case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond2_stb = 1'b0; //comparison disabled
- 3'b001: match_cond2_stb = 1'b1; // insn fetch EA
- default:match_cond2_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 2
-//
-always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
- casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match2 = 1'b0;
- 4'b1_001: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} ==
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_010: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_011: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <=
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_100: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_101: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >=
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_110: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} !=
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- endcase
-
-//
-// Watchpoint 2
-//
-always @(dmr1 or match2 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW2])
- 2'b00: wp[2] = match2;
- 2'b01: wp[2] = match2 & wp[1];
- 2'b10: wp[2] = match2 | wp[1];
- 2'b11: wp[2] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 3)
-//
-always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond3_ct = id_pc; // insn fetch EA
- 3'b010: match_cond3_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond3_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond3_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond3_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond3_ct = dcpu_adr_i; // load/store EA
- default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 3)
-//
-always @(dcr3 or dcpu_cycstb_i)
- case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond3_stb = 1'b0; //comparison disabled
- 3'b001: match_cond3_stb = 1'b1; // insn fetch EA
- default:match_cond3_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 3
-//
-always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
- casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match3 = 1'b0;
- 4'b1_001: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} ==
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_010: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_011: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <=
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_100: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_101: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >=
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_110: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} !=
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- endcase
-
-//
-// Watchpoint 3
-//
-always @(dmr1 or match3 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW3])
- 2'b00: wp[3] = match3;
- 2'b01: wp[3] = match3 & wp[2];
- 2'b10: wp[3] = match3 | wp[2];
- 2'b11: wp[3] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 4)
-//
-always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond4_ct = id_pc; // insn fetch EA
- 3'b010: match_cond4_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond4_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond4_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond4_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond4_ct = dcpu_adr_i; // load/store EA
- default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 4)
-//
-always @(dcr4 or dcpu_cycstb_i)
- case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond4_stb = 1'b0; //comparison disabled
- 3'b001: match_cond4_stb = 1'b1; // insn fetch EA
- default:match_cond4_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 4
-//
-always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
- casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match4 = 1'b0;
- 4'b1_001: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} ==
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_010: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_011: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <=
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_100: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_101: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >=
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_110: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} !=
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- endcase
-
-//
-// Watchpoint 4
-//
-always @(dmr1 or match4 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW4])
- 2'b00: wp[4] = match4;
- 2'b01: wp[4] = match4 & wp[3];
- 2'b10: wp[4] = match4 | wp[3];
- 2'b11: wp[4] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 5)
-//
-always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond5_ct = id_pc; // insn fetch EA
- 3'b010: match_cond5_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond5_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond5_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond5_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond5_ct = dcpu_adr_i; // load/store EA
- default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 5)
-//
-always @(dcr5 or dcpu_cycstb_i)
- case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond5_stb = 1'b0; //comparison disabled
- 3'b001: match_cond5_stb = 1'b1; // insn fetch EA
- default:match_cond5_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 5
-//
-always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
- casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match5 = 1'b0;
- 4'b1_001: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} ==
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_010: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_011: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <=
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_100: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_101: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >=
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_110: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} !=
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- endcase
-
-//
-// Watchpoint 5
-//
-always @(dmr1 or match5 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW5])
- 2'b00: wp[5] = match5;
- 2'b01: wp[5] = match5 & wp[4];
- 2'b10: wp[5] = match5 | wp[4];
- 2'b11: wp[5] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 6)
-//
-always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond6_ct = id_pc; // insn fetch EA
- 3'b010: match_cond6_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond6_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond6_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond6_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond6_ct = dcpu_adr_i; // load/store EA
- default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 6)
-//
-always @(dcr6 or dcpu_cycstb_i)
- case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond6_stb = 1'b0; //comparison disabled
- 3'b001: match_cond6_stb = 1'b1; // insn fetch EA
- default:match_cond6_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 6
-//
-always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
- casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match6 = 1'b0;
- 4'b1_001: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} ==
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_010: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_011: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <=
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_100: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_101: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >=
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_110: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} !=
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- endcase
-
-//
-// Watchpoint 6
-//
-always @(dmr1 or match6 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW6])
- 2'b00: wp[6] = match6;
- 2'b01: wp[6] = match6 & wp[5];
- 2'b10: wp[6] = match6 | wp[5];
- 2'b11: wp[6] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 7)
-//
-always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond7_ct = id_pc; // insn fetch EA
- 3'b010: match_cond7_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond7_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond7_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond7_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond7_ct = dcpu_adr_i; // load/store EA
- default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 7)
-//
-always @(dcr7 or dcpu_cycstb_i)
- case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond7_stb = 1'b0; //comparison disabled
- 3'b001: match_cond7_stb = 1'b1; // insn fetch EA
- default:match_cond7_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 7
-//
-always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
- casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match7 = 1'b0;
- 4'b1_001: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} ==
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_010: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_011: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <=
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_100: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_101: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >=
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_110: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} !=
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- endcase
-
-//
-// Watchpoint 7
-//
-always @(dmr1 or match7 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW7])
- 2'b00: wp[7] = match7;
- 2'b01: wp[7] = match7 & wp[6];
- 2'b10: wp[7] = match7 | wp[6];
- 2'b11: wp[7] = 1'b0;
- endcase
-
-//
-// Increment Watchpoint Counter 0
-//
-always @(wp or dmr2)
- if (dmr2[`OR1200_DU_DMR2_WCE0])
- incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
- else
- incr_wpcntr0 = 1'b0;
-
-//
-// Match Condition Watchpoint Counter 0
-//
-always @(dwcr0)
- if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
- wpcntr0_match = 1'b1;
- else
- wpcntr0_match = 1'b0;
-
-
-//
-// Watchpoint 8
-//
-always @(dmr1 or wpcntr0_match or wp)
- case (dmr1[`OR1200_DU_DMR1_CW8])
- 2'b00: wp[8] = wpcntr0_match;
- 2'b01: wp[8] = wpcntr0_match & wp[7];
- 2'b10: wp[8] = wpcntr0_match | wp[7];
- 2'b11: wp[8] = 1'b0;
- endcase
-
-
-//
-// Increment Watchpoint Counter 1
-//
-always @(wp or dmr2)
- if (dmr2[`OR1200_DU_DMR2_WCE1])
- incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
- else
- incr_wpcntr1 = 1'b0;
-
-//
-// Match Condition Watchpoint Counter 1
-//
-always @(dwcr1)
- if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
- wpcntr1_match = 1'b1;
- else
- wpcntr1_match = 1'b0;
-
-//
-// Watchpoint 9
-//
-always @(dmr1 or wpcntr1_match or wp)
- case (dmr1[`OR1200_DU_DMR1_CW9])
- 2'b00: wp[9] = wpcntr1_match;
- 2'b01: wp[9] = wpcntr1_match & wp[8];
- 2'b10: wp[9] = wpcntr1_match | wp[8];
- 2'b11: wp[9] = 1'b0;
- endcase
-
-//
-// Watchpoint 10
-//
-always @(dmr1 or dbg_ewt_i or wp)
- case (dmr1[`OR1200_DU_DMR1_CW10])
- 2'b00: wp[10] = dbg_ewt_i;
- 2'b01: wp[10] = dbg_ewt_i & wp[9];
- 2'b10: wp[10] = dbg_ewt_i | wp[9];
- 2'b11: wp[10] = 1'b0;
- endcase
-
-`endif
-
-//
-// Watchpoints can cause trap exception
-//
-`ifdef OR1200_DU_HWBKPTS
-assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]) | du_hwbkpt_hold | (dbg_bp_r & ~dsr[`OR1200_DU_DSR_TE]);
-`else
-assign du_hwbkpt = 1'b0;
-`endif
-
-// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- du_hwbkpt_hold <= 1'b0;
- else if (du_hwbkpt & ex_freeze)
- du_hwbkpt_hold <= 1'b1;
- else if (!ex_freeze)
- du_hwbkpt_hold <= 1'b0;
-
-`ifdef OR1200_DU_TB_IMPLEMENTED
-//
-// Simple trace buffer
-// (right now hardcoded for Xilinx Virtex FPGAs)
-//
-// Stores last 256 instruction addresses, instruction
-// machine words and ALU results
-//
-
-//
-// Trace buffer write enable
-//
-assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
-
-//
-// Trace buffer write address pointer
-//
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- tb_wadr <= 8'h00;
- else if (tb_enw)
- tb_wadr <= tb_wadr + 8'd1;
-
-//
-// Free running counter (time stamp)
-//
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- tb_timstmp <= 32'h00000000;
- else if (!dbg_bp_r)
- tb_timstmp <= tb_timstmp + 32'd1;
-
-//
-// Trace buffer RAMs
-//
-
-or1200_dpram_256x32 tbia_ram(
- .clk_a(clk),
- .rst_a(1'b0),
- .addr_a(spr_addr[7:0]),
- .ce_a(1'b1),
- .oe_a(1'b1),
- .do_a(tbia_dat_o),
-
- .clk_b(clk),
- .rst_b(1'b0),
- .addr_b(tb_wadr),
- .di_b(spr_dat_npc),
- .ce_b(1'b1),
- .we_b(tb_enw)
-
-);
-
-or1200_dpram_256x32 tbim_ram(
- .clk_a(clk),
- .rst_a(1'b0),
- .addr_a(spr_addr[7:0]),
- .ce_a(1'b1),
- .oe_a(1'b1),
- .do_a(tbim_dat_o),
-
- .clk_b(clk),
- .rst_b(1'b0),
- .addr_b(tb_wadr),
- .di_b(ex_insn),
- .ce_b(1'b1),
- .we_b(tb_enw)
-);
-
-or1200_dpram_256x32 tbar_ram(
- .clk_a(clk),
- .rst_a(1'b0),
- .addr_a(spr_addr[7:0]),
- .ce_a(1'b1),
- .oe_a(1'b1),
- .do_a(tbar_dat_o),
-
- .clk_b(clk),
- .rst_b(1'b0),
- .addr_b(tb_wadr),
- .di_b(rf_dataw),
- .ce_b(1'b1),
- .we_b(tb_enw)
-);
-
-or1200_dpram_256x32 tbts_ram(
- .clk_a(clk),
- .rst_a(1'b0),
- .addr_a(spr_addr[7:0]),
- .ce_a(1'b1),
- .oe_a(1'b1),
- .do_a(tbts_dat_o),
-
- .clk_b(clk),
- .rst_b(1'b0),
- .addr_b(tb_wadr),
- .di_b(tb_timstmp),
- .ce_b(1'b1),
- .we_b(tb_enw)
-);
-
-`else
-
-assign tbia_dat_o = 32'h0000_0000;
-assign tbim_dat_o = 32'h0000_0000;
-assign tbar_dat_o = 32'h0000_0000;
-assign tbts_dat_o = 32'h0000_0000;
-
-`endif // OR1200_DU_TB_IMPLEMENTED
-
-`else // OR1200_DU_IMPLEMENTED
-
-//
-// When DU is not implemented, drive all outputs as would when DU is disabled
-//
-assign dbg_bp_o = 1'b0;
-assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
-assign du_dmr1 = {25{1'b0}};
-assign du_hwbkpt = 1'b0;
-
-//
-// Read DU registers
-//
-`ifdef OR1200_DU_READREGS
-assign spr_dat_o = 32'h0000_0000;
-`ifdef OR1200_DU_UNUSED_ZERO
-`endif
-`endif
-
-`endif
-
-endmodule
diff --git a/autotests/input/syntax/verilog/results/or1200_dc_fsm.v.reference.html b/autotests/input/syntax/verilog/results/or1200_dc_fsm.v.reference.html
deleted file mode 100644
index 25f2053e..00000000
--- a/autotests/input/syntax/verilog/results/or1200_dc_fsm.v.reference.html
+++ /dev/null
@@ -1,577 +0,0 @@
-
-
-
-
-
-
-or1200_dc_fsm.v
-
-
-
-
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// OR1200's DC FSM ////
-//// ////
-//// This file is part of the OpenRISC 1200 project ////
-//// http://opencores.org/project,or1k ////
-//// ////
-//// Description ////
-//// Data cache state machine ////
-//// ////
-//// To Do: ////
-//// - Test error during line read or write ////
-//// ////
-//// Author(s): ////
-//// - Damjan Lampret, lampret@opencores.org ////
-//// - Julius Baxter, julius@opencores.org ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// $Log: or1200_dc_fsm.v,v $
-// Revision 2.0 2010/06/30 11:00:00 ORSoC
-// Minor update:
-// Bugs fixed.
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "or1200_defines.v"
-
-`define OR1200_DCFSM_IDLE 3'd0
-`define OR1200_DCFSM_CLOADSTORE 3'd1
-`define OR1200_DCFSM_LOOP2 3'd2
-`define OR1200_DCFSM_LOOP3 3'd3
-`define OR1200_DCFSM_LOOP4 3'd4
-`define OR1200_DCFSM_FLUSH5 3'd5
-`define OR1200_DCFSM_INV6 3'd6
-`define OR1200_DCFSM_WAITSPRCS7 3'd7
-
-
-
-//
-// Data cache FSM for cache line of 16 bytes (4x singleword)
-//
-
-module or1200_dc_fsm
- (
- // Clock and reset
- clk, rst,
-
- // Internal i/f to top level DC
- dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
- tagcomp_miss, biudata_valid, biudata_error, lsu_addr,
- dcram_we, biu_read, biu_write, biu_do_sel, dcram_di_sel, first_hit_ack,
- first_miss_ack, first_miss_err, burst, tag_we, tag_valid, dc_addr,
- dc_no_writethrough, tag_dirty, dirty, tag, tag_v, dc_block_flush,
- dc_block_writeback, spr_dat_i, mtspr_dc_done, spr_cswe
- );
-
- //
- // I/O
- //
- input clk;
- input rst;
- input dc_en;
- input dcqmem_cycstb_i;
- input dcqmem_ci_i;
- input dcqmem_we_i;
- input [3:0] dcqmem_sel_i;
- input tagcomp_miss;
- input biudata_valid;
- input biudata_error;
- input [31:0] lsu_addr;
- output [3:0] dcram_we;
- output biu_read;
- output biu_write;
- output dcram_di_sel;
- output biu_do_sel;
- output first_hit_ack;
- output first_miss_ack;
- output first_miss_err;
- output burst;
- output tag_we;
- output tag_valid;
- output [31:0] dc_addr;
- input dc_no_writethrough;
- output tag_dirty;
- input dirty;
- input [`OR1200_DCTAG_W-2:0] tag;
- input tag_v;
- input dc_block_flush;
- input dc_block_writeback;
- input [31:0] spr_dat_i;
- output mtspr_dc_done;
- input spr_cswe;
-
-
- //
- // Internal wires and regs
- //
- reg [31:0] addr_r;
- reg [2:0] state;
- reg [`OR1200_DCLS-1:0] cnt;
- reg hitmiss_eval;
- reg store;
- reg load;
- reg cache_inhibit;
- reg cache_miss;
- reg cache_dirty_needs_writeback;
- reg did_early_load_ack;
- reg cache_spr_block_flush;
- reg cache_spr_block_writeback;
- reg cache_wb;
- wire load_hit_ack;
- wire load_miss_ack;
- wire load_inhibit_ack;
- wire store_hit_ack;
- wire store_hit_writethrough_ack;
- wire store_miss_writethrough_ack;
- wire store_inhibit_ack;
- wire store_miss_ack;
- wire dcram_we_after_line_load;
- wire dcram_we_during_line_load;
- wire tagram_we_end_of_loadstore_loop;
- wire tagram_dirty_bit_set;
- wire writethrough;
- wire cache_inhibit_with_eval;
- wire [(`OR1200_DCLS-1)-2:0] next_addr_word;
-
- //
- // Cache inhibit
- //
-
- // Indicates whether cache is inhibited, during hitmiss_eval and after
- assign cache_inhibit_with_eval = (hitmiss_eval & dcqmem_ci_i) |
- (!hitmiss_eval & cache_inhibit);
-
- //
- // Generate of DCRAM write enables
- //
-
- // WE when non-writethrough, and had to wait for a line to load.
- assign dcram_we_after_line_load = (state == `OR1200_DCFSM_LOOP3) &
- dcqmem_we_i & !cache_dirty_needs_writeback &
- !did_early_load_ack;
-
- // WE when receiving the data cache line
- assign dcram_we_during_line_load = (state == `OR1200_DCFSM_LOOP2) & load &
- biudata_valid;
-
- assign dcram_we =(// Write when hit - make sure it is only when hit - could
- // maybe be doing write through and don't want to corrupt
- // cache lines corresponding to the writethrough addr_r.
- ({4{store_hit_ack | store_hit_writethrough_ack}} |
- // Write after load of line
- {4{dcram_we_after_line_load}}) &
- dcqmem_sel_i ) |
- // Write during load
- {4{dcram_we_during_line_load}};
-
- //
- // Tag RAM signals
- //
-
- // WE to tag RAM when we finish loading a line.
- assign tagram_we_end_of_loadstore_loop = ((state==`OR1200_DCFSM_LOOP2) &
- biudata_valid & !(|cnt));
-
-`ifndef OR1200_DC_WRITETHROUGH
- // No writethrough, so mark a line dirty whenever we write to it
- assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
-
- // Generate done signal for MTSPR instructions that may block execution
- assign mtspr_dc_done = // Either DC disabled or we're not selected, or
- !dc_en | !spr_cswe |
- // Requested address not valid or writeback and !dirty
- ((state==`OR1200_DCFSM_FLUSH5) &
- (!tag_v | (cache_spr_block_writeback & !dirty))) |
- // Writeback or flush is finished
- ((state==`OR1200_DCFSM_LOOP3) &
- (cache_spr_block_flush | cache_spr_block_writeback))|
- // Invalidate of clean line finished
- ((state==`OR1200_DCFSM_INV6) & cache_spr_block_flush);
-
-
-`else
- `ifdef OR1200_DC_NOSTACKWRITETHROUGH
- // For dirty bit setting when having writethrough but not for stack
- assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
- `else
- // Lines will never be dirty if always writethrough
- assign tagram_dirty_bit_set = 0;
- `endif
-
- assign mtspr_dc_done = 1'b1;
-
-`endif
-
- assign tag_dirty = tagram_dirty_bit_set;
-
- // WE to tag RAM
- assign tag_we = tagram_we_end_of_loadstore_loop |
- tagram_dirty_bit_set | (state == `OR1200_DCFSM_INV6);
-
-
- // Valid bit
- // Set valid when end of line load, or marking dirty (is still valid)
- assign tag_valid = ( tagram_we_end_of_loadstore_loop &
- (load | (store & cache_spr_block_writeback)) ) |
- tagram_dirty_bit_set;
-
-
-
- //
- // BIU read and write
- //
-
- assign biu_read = // Bus read request when:
- // 1) Have a miss and not dirty or a load with inhibit
- ((state == `OR1200_DCFSM_CLOADSTORE) &
- (((hitmiss_eval & tagcomp_miss & !dirty &
- !(store & writethrough)) |
- (load & cache_inhibit_with_eval)) & dcqmem_cycstb_i)) |
- // 2) In the loop and loading
- ((state == `OR1200_DCFSM_LOOP2) & load);
-
-
- assign biu_write = // Bus write request when:
- // 1) Have a miss and dirty or store with inhibit
- ((state == `OR1200_DCFSM_CLOADSTORE) &
- (((hitmiss_eval & tagcomp_miss & dirty) |
- (store & writethrough)) |
- (store & cache_inhibit_with_eval)) & dcqmem_cycstb_i) |
- // 2) In the loop and storing
- ((state == `OR1200_DCFSM_LOOP2) & store);
-
- //
- // Select for data to actual cache RAM (from LSU or BIU)
- //
- // Data to DCRAM - from external bus when loading (from IU when store)
- assign dcram_di_sel = load;
- // Data to external bus - always from IU except in case of bursting back
- // the line to memory. (1 selects DCRAM)
- assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;
-
- // 3-bit wire for calculating next word of burst write, depending on
- // line size of data cache.
- assign next_addr_word = addr_r[`OR1200_DCLS-1:2] + 1;
-
- // Address to cache RAM (tag address also derived from this)
- assign dc_addr =
- // First check if we've got a block flush or WB op
- ((dc_block_flush & !cache_spr_block_flush) |
- (dc_block_writeback & !cache_spr_block_writeback)) ?
- spr_dat_i :
- (state==`OR1200_DCFSM_FLUSH5) ? addr_r:
- // If no SPR action, then always put out address from LSU
- (state==`OR1200_DCFSM_IDLE | hitmiss_eval) ? lsu_addr :
- // Next, if in writeback loop, when ACKed must immediately
- // output next word address (the RAM address takes a cycle
- // to increment, but it's needed immediately for burst)
- // otherwise, output our registered address.
- (state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ?
- {addr_r[31:`OR1200_DCLS], next_addr_word, 2'b00} : addr_r;
-
-`ifdef OR1200_DC_WRITETHROUGH
- `ifdef OR1200_DC_NOSTACKWRITETHROUGH
- assign writethrough = !dc_no_writethrough;
- `else
- assign writethrough = 1;
- `endif
-`else
- assign writethrough = 0;
-`endif
-
- //
- // ACK generation for LSU
- //
-
- // ACK for when it's a cache hit
- assign first_hit_ack = load_hit_ack | store_hit_ack |
- store_hit_writethrough_ack |
- store_miss_writethrough_ack |
- store_inhibit_ack | store_miss_ack ;
-
- // ACK for when it's a cache miss - load only, is used in MUX for data back
- // LSU straight off external data bus. In
- // this was is also used for cache inhibit
- // loads.
- // first_hit_ack takes precedence over first_miss_ack
- assign first_miss_ack = ~first_hit_ack & (load_miss_ack | load_inhibit_ack);
-
- // ACK cache hit on load
- assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
-
- // ACK cache hit on store, no writethrough
- assign store_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
- store & !writethrough;
-
- // ACK cache hit on store with writethrough
- assign store_hit_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- !cache_miss & !cache_inhibit &
- store & writethrough & biudata_valid;
-
- // ACK cache miss on store with writethrough
- assign store_miss_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- cache_miss & !cache_inhibit &
- store & writethrough & biudata_valid;
-
- // ACK store when cacheinhibit
- assign store_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- store & cache_inhibit & biudata_valid;
-
-
- // Get the _early_ ack on first ACK back from wishbone during load only
- // Condition is that we're in the loop - that it's the first ack we get (can
- // tell from value of cnt), and we're loading a line to read from it (not
- // loading to write to it, in the case of a write without writethrough.)
- assign load_miss_ack = ((state== `OR1200_DCFSM_LOOP2) & load &
- (cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid &
- !(dcqmem_we_i & !writethrough));
-
- assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
- load & cache_inhibit & biudata_valid;
-
- // This will be case of write through disabled, and had to load a line.
- assign store_miss_ack = dcram_we_after_line_load;
-
- assign first_miss_err = biudata_error & dcqmem_cycstb_i;
-
- // Signal burst when in the load/store loop. We will always try to burst.
- assign burst = (state == `OR1200_DCFSM_LOOP2);
-
- //
- // Main DC FSM
- //
- always @(posedge clk or `OR1200_RST_EVENT rst) begin
- if (rst == `OR1200_RST_VALUE) begin
- state <= `OR1200_DCFSM_IDLE;
- addr_r <= 32'd0;
- hitmiss_eval <= 1'b0;
- store <= 1'b0;
- load <= 1'b0;
- cnt <= `OR1200_DCLS'd0;
- cache_miss <= 1'b0;
- cache_dirty_needs_writeback <= 1'b0;
- cache_inhibit <= 1'b0;
- did_early_load_ack <= 1'b0;
- cache_spr_block_flush <= 1'b0;
- cache_spr_block_writeback <= 1'b0;
- end
- else
- case (state) // synopsys parallel_case
-
- `OR1200_DCFSM_IDLE : begin
- if (dc_en & (dc_block_flush | dc_block_writeback))
- begin
- cache_spr_block_flush <= dc_block_flush;
- cache_spr_block_writeback <= dc_block_writeback;
- hitmiss_eval <= 1'b1;
- state <= `OR1200_DCFSM_FLUSH5;
- addr_r <= spr_dat_i;
- end
- else if (dc_en & dcqmem_cycstb_i)
- begin
- state <= `OR1200_DCFSM_CLOADSTORE;
- hitmiss_eval <= 1'b1;
- store <= dcqmem_we_i;
- load <= !dcqmem_we_i;
- end
-
-
- end // case: `OR1200_DCFSM_IDLE
-
- `OR1200_DCFSM_CLOADSTORE: begin
- hitmiss_eval <= 1'b0;
- if (hitmiss_eval) begin
- cache_inhibit <= dcqmem_ci_i; // Check for cache inhibit here
- cache_miss <= tagcomp_miss;
- cache_dirty_needs_writeback <= dirty;
- addr_r <= lsu_addr;
- end
-
- // Evaluate any cache line load/stores in first cycle:
- //
- if (hitmiss_eval & tagcomp_miss & !(store & writethrough) &
- !dcqmem_ci_i)
- begin
- // Miss - first either:
- // 1) write back dirty line
- if (dirty) begin
- // Address for writeback
- addr_r <= {tag, lsu_addr[`OR1200_DCINDXH:2],2'd0};
- load <= 1'b0;
- store <= 1'b1;
-`ifdef OR1200_VERBOSE
- $display("%t: dcache miss and dirty", $time);
-`endif
- end
- // 2) load requested line
- else begin
- addr_r <= lsu_addr;
- load <= 1'b1;
- store <= 1'b0;
- end // else: !if(dirty)
- state <= `OR1200_DCFSM_LOOP2;
- // Set the counter for the burst accesses
- cnt <= ((1 << `OR1200_DCLS) - 4);
- end
- else if (// Strobe goes low
- !dcqmem_cycstb_i |
- // Cycle finishes
- (!hitmiss_eval & (biudata_valid | biudata_error)) |
- // Cache hit in first cycle....
- (hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
- // .. and you're not doing a writethrough store..
- !(store & writethrough))) begin
- state <= `OR1200_DCFSM_IDLE;
- load <= 1'b0;
- store <= 1'b0;
- cache_inhibit <= 1'b0;
- cache_dirty_needs_writeback <= 1'b0;
- end
- end // case: `OR1200_DCFSM_CLOADSTORE
-
- `OR1200_DCFSM_LOOP2 : begin // loop/abort
- if (!dc_en| biudata_error) begin
- state <= `OR1200_DCFSM_IDLE;
- load <= 1'b0;
- store <= 1'b0;
- cnt <= `OR1200_DCLS'd0;
- end
- if (biudata_valid & (|cnt)) begin
- cnt <= cnt - 4;
- addr_r[`OR1200_DCLS-1:2] <= addr_r[`OR1200_DCLS-1:2] + 1;
- end
- else if (biudata_valid & !(|cnt)) begin
- state <= `OR1200_DCFSM_LOOP3;
- addr_r <= lsu_addr;
- load <= 1'b0;
- store <= 1'b0;
- end
-
- // Track if we did an early ack during a load
- if (load_miss_ack)
- did_early_load_ack <= 1'b1;
-
-
- end // case: `OR1200_DCFSM_LOOP2
-
- `OR1200_DCFSM_LOOP3: begin // figure out next step
- if (cache_dirty_needs_writeback) begin
- // Just did store of the dirty line so now load new one
- load <= 1'b1;
- // Set the counter for the burst accesses
- cnt <= ((1 << `OR1200_DCLS) - 4);
- // Address of line to be loaded
- addr_r <= lsu_addr;
- cache_dirty_needs_writeback <= 1'b0;
- state <= `OR1200_DCFSM_LOOP2;
- end // if (cache_dirty_needs_writeback)
- else if (cache_spr_block_flush | cache_spr_block_writeback) begin
- // Just wrote back the line to memory, we're finished.
- cache_spr_block_flush <= 1'b0;
- cache_spr_block_writeback <= 1'b0;
- state <= `OR1200_DCFSM_WAITSPRCS7;
- end
- else begin
- // Just loaded a new line, finish up
- did_early_load_ack <= 1'b0;
- state <= `OR1200_DCFSM_LOOP4;
- end
- end // case: `OR1200_DCFSM_LOOP3
-
- `OR1200_DCFSM_LOOP4: begin
- state <= `OR1200_DCFSM_IDLE;
- end
-
- `OR1200_DCFSM_FLUSH5: begin
- hitmiss_eval <= 1'b0;
- if (hitmiss_eval & !tag_v)
- begin
- // Not even cached, just ignore
- cache_spr_block_flush <= 1'b0;
- cache_spr_block_writeback <= 1'b0;
- state <= `OR1200_DCFSM_WAITSPRCS7;
- end
- else if (hitmiss_eval & tag_v)
- begin
- // Tag is valid - what do we do?
- if ((cache_spr_block_flush | cache_spr_block_writeback) &
- dirty) begin
- // Need to writeback
- // Address for writeback (spr_dat_i has already changed so
- // use line number from addr_r)
- addr_r <= {tag, addr_r[`OR1200_DCINDXH:2],2'd0};
- load <= 1'b0;
- store <= 1'b1;
-`ifdef OR1200_VERBOSE
- $display("%t: block flush: dirty block", $time);
-`endif
- state <= `OR1200_DCFSM_LOOP2;
- // Set the counter for the burst accesses
- cnt <= ((1 << `OR1200_DCLS) - 4);
- end
- else if (cache_spr_block_flush & !dirty)
- begin
- // Line not dirty, just need to invalidate
- state <= `OR1200_DCFSM_INV6;
- end // else: !if(dirty)
- else if (cache_spr_block_writeback & !dirty)
- begin
- // Nothing to do - line is valid but not dirty
- cache_spr_block_writeback <= 1'b0;
- state <= `OR1200_DCFSM_WAITSPRCS7;
- end
- end // if (hitmiss_eval & tag_v)
- end
- `OR1200_DCFSM_INV6: begin
- cache_spr_block_flush <= 1'b0;
- // Wait until SPR CS goes low before going back to idle
- if (!spr_cswe)
- state <= `OR1200_DCFSM_IDLE;
- end
- `OR1200_DCFSM_WAITSPRCS7: begin
- // Wait until SPR CS goes low before going back to idle
- if (!spr_cswe)
- state <= `OR1200_DCFSM_IDLE;
- end
-
- endcase // case (state)
-
- end // always @ (posedge clk or `OR1200_RST_EVENT rst)
-
-
-endmodule
-
-
-
diff --git a/autotests/input/syntax/verilog/results/or1200_du.v.reference.html b/autotests/input/syntax/verilog/results/or1200_du.v.reference.html
deleted file mode 100644
index 7fb1cf57..00000000
--- a/autotests/input/syntax/verilog/results/or1200_du.v.reference.html
+++ /dev/null
@@ -1,1817 +0,0 @@
-
-
-
-
-
-
-or1200_du.v
-
-
-
-
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// OR1200's Debug Unit ////
-//// ////
-//// This file is part of the OpenRISC 1200 project ////
-//// http://www.opencores.org/project,or1k ////
-//// ////
-//// Description ////
-//// Basic OR1200 debug unit. ////
-//// ////
-//// To Do: ////
-//// - make it smaller and faster ////
-//// ////
-//// Author(s): ////
-//// - Damjan Lampret, lampret@opencores.org ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-//
-// $Log: or1200_du.v,v $
-// Revision 2.0 2010/06/30 11:00:00 ORSoC
-// Minor update:
-// Bugs fixed.
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "or1200_defines.v"
-
-//
-// Debug unit
-//
-
-module or1200_du(
- // RISC Internal Interface
- clk, rst,
- dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
- dcpu_dat_dc, icpu_cycstb_i,
- ex_freeze, branch_op, ex_insn, id_pc,
- spr_dat_npc, rf_dataw,
- du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
- du_read, du_write, du_except_stop, du_hwbkpt, du_flush_pipe,
- spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
-
- // External Debug Interface
- dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
- dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
-);
-
-parameter dw = `OR1200_OPERAND_WIDTH;
-parameter aw = `OR1200_OPERAND_WIDTH;
-
-//
-// I/O
-//
-
-//
-// RISC Internal Interface
-//
-input clk; // Clock
-input rst; // Reset
-input dcpu_cycstb_i; // LSU status
-input dcpu_we_i; // LSU status
-input [31:0] dcpu_adr_i; // LSU addr
-input [31:0] dcpu_dat_lsu; // LSU store data
-input [31:0] dcpu_dat_dc; // LSU load data
-input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
-input ex_freeze; // EX stage freeze
-input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
-input [dw-1:0] ex_insn; // EX insn
-input [31:0] id_pc; // insn fetch EA
-input [31:0] spr_dat_npc; // Next PC (for trace)
-input [31:0] rf_dataw; // ALU result (for trace)
-output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
-output [24: 0] du_dmr1;
-output du_stall; // Debug Unit Stall
-output [aw-1:0] du_addr; // Debug Unit Address
-input [dw-1:0] du_dat_i; // Debug Unit Data In
-output [dw-1:0] du_dat_o; // Debug Unit Data Out
-output du_read; // Debug Unit Read Enable
-output du_write; // Debug Unit Write Enable
-input [13:0] du_except_stop; // Exception masked by DSR
-output du_hwbkpt; // Cause trap exception (HW Breakpoints)
-output du_flush_pipe; // Cause pipeline flush and pc<-npc
-input spr_cs; // SPR Chip Select
-input spr_write; // SPR Read/Write
-input [aw-1:0] spr_addr; // SPR Address
-input [dw-1:0] spr_dat_i; // SPR Data Input
-output [dw-1:0] spr_dat_o; // SPR Data Output
-
-//
-// External Debug Interface
-//
-input dbg_stall_i; // External Stall Input
-input dbg_ewt_i; // External Watchpoint Trigger Input
-output [3:0] dbg_lss_o; // External Load/Store Unit Status
-output [1:0] dbg_is_o; // External Insn Fetch Status
-output [10:0] dbg_wp_o; // Watchpoints Outputs
-output dbg_bp_o; // Breakpoint Output
-input dbg_stb_i; // External Address/Data Strobe
-input dbg_we_i; // External Write Enable
-input [aw-1:0] dbg_adr_i; // External Address Input
-input [dw-1:0] dbg_dat_i; // External Data Input
-output [dw-1:0] dbg_dat_o; // External Data Output
-output dbg_ack_o; // External Data Acknowledge (not WB compatible)
-reg [dw-1:0] dbg_dat_o; // External Data Output
-reg dbg_ack_o; // External Data Acknowledge (not WB compatible)
-
-
-//
-// Some connections go directly from the CPU through DU to Debug I/F
-//
-`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
-assign dbg_lss_o = 4'b0000;
-
-reg [1:0] dbg_is_o;
-//
-// Show insn activity (temp, must be removed)
-//
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dbg_is_o <= 2'b00;
- else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
- dbg_is_o <= ~dbg_is_o;
-`ifdef UNUSED
-assign dbg_is_o = 2'b00;
-`endif
-`else
-assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
-assign dbg_is_o = {1'b0, icpu_cycstb_i};
-`endif
-assign dbg_wp_o = 11'b000_0000_0000;
-
-//
-// Some connections go directly from Debug I/F through DU to the CPU
-//
-assign du_stall = dbg_stall_i;
-assign du_addr = dbg_adr_i;
-assign du_dat_o = dbg_dat_i;
-assign du_read = dbg_stb_i && !dbg_we_i;
-assign du_write = dbg_stb_i && dbg_we_i;
-
-//
-// After a sw breakpoint, the replaced instruction need to be executed.
-// We flush the entire pipeline and set the pc to the current address
-// to execute the restored address.
-//
-
-reg du_flush_pipe_r;
-reg dbg_stall_i_r;
-
-assign du_flush_pipe = du_flush_pipe_r;
-
-//
-// Register du_flush_pipe
-//
-always @(posedge clk or `OR1200_RST_EVENT rst) begin
- if (rst == `OR1200_RST_VALUE) begin
- du_flush_pipe_r <= 1'b0;
- end
- else begin
- du_flush_pipe_r <= (dbg_stall_i_r && !dbg_stall_i && |du_except_stop);
- end
-end
-
-//
-// Detect dbg_stall falling edge
-//
-always @(posedge clk or `OR1200_RST_EVENT rst) begin
- if (rst == `OR1200_RST_VALUE) begin
- dbg_stall_i_r <= 1'b0;
- end
- else begin
- dbg_stall_i_r <= dbg_stall_i;
- end
-end
-
-reg dbg_ack;
-//
-// Generate acknowledge -- just delay stb signal
-//
-always @(posedge clk or `OR1200_RST_EVENT rst) begin
- if (rst == `OR1200_RST_VALUE) begin
- dbg_ack <= 1'b0;
- dbg_ack_o <= 1'b0;
- end
- else begin
- dbg_ack <= dbg_stb_i; // valid when du_dat_i
- dbg_ack_o <= dbg_ack & dbg_stb_i; // valid when dbg_dat_o
- end
-end
-
-//
-// Register data output
-//
-always @(posedge clk)
- dbg_dat_o <= du_dat_i;
-
-`ifdef OR1200_DU_IMPLEMENTED
-
-//
-// Debug Mode Register 1
-//
-`ifdef OR1200_DU_DMR1
-reg [24:0] dmr1; // DMR1 implemented
-`else
-wire [24:0] dmr1; // DMR1 not implemented
-`endif
-assign du_dmr1 = dmr1;
-
-//
-// Debug Mode Register 2
-//
-`ifdef OR1200_DU_DMR2
-reg [23:0] dmr2; // DMR2 implemented
-`else
-wire [23:0] dmr2; // DMR2 not implemented
-`endif
-
-//
-// Debug Stop Register
-//
-`ifdef OR1200_DU_DSR
-reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
-`else
-wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
-`endif
-
-//
-// Debug Reason Register
-//
-`ifdef OR1200_DU_DRR
-reg [13:0] drr; // DRR implemented
-`else
-wire [13:0] drr; // DRR not implemented
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR0
-reg [31:0] dvr0;
-`else
-wire [31:0] dvr0;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR1
-reg [31:0] dvr1;
-`else
-wire [31:0] dvr1;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR2
-reg [31:0] dvr2;
-`else
-wire [31:0] dvr2;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR3
-reg [31:0] dvr3;
-`else
-wire [31:0] dvr3;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR4
-reg [31:0] dvr4;
-`else
-wire [31:0] dvr4;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR5
-reg [31:0] dvr5;
-`else
-wire [31:0] dvr5;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR6
-reg [31:0] dvr6;
-`else
-wire [31:0] dvr6;
-`endif
-
-//
-// Debug Value Register N
-//
-`ifdef OR1200_DU_DVR7
-reg [31:0] dvr7;
-`else
-wire [31:0] dvr7;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR0
-reg [7:0] dcr0;
-`else
-wire [7:0] dcr0;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR1
-reg [7:0] dcr1;
-`else
-wire [7:0] dcr1;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR2
-reg [7:0] dcr2;
-`else
-wire [7:0] dcr2;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR3
-reg [7:0] dcr3;
-`else
-wire [7:0] dcr3;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR4
-reg [7:0] dcr4;
-`else
-wire [7:0] dcr4;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR5
-reg [7:0] dcr5;
-`else
-wire [7:0] dcr5;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR6
-reg [7:0] dcr6;
-`else
-wire [7:0] dcr6;
-`endif
-
-//
-// Debug Control Register N
-//
-`ifdef OR1200_DU_DCR7
-reg [7:0] dcr7;
-`else
-wire [7:0] dcr7;
-`endif
-
-//
-// Debug Watchpoint Counter Register 0
-//
-`ifdef OR1200_DU_DWCR0
-reg [31:0] dwcr0;
-`else
-wire [31:0] dwcr0;
-`endif
-
-//
-// Debug Watchpoint Counter Register 1
-//
-`ifdef OR1200_DU_DWCR1
-reg [31:0] dwcr1;
-`else
-wire [31:0] dwcr1;
-`endif
-
-//
-// Internal wires
-//
-wire dmr1_sel; // DMR1 select
-wire dmr2_sel; // DMR2 select
-wire dsr_sel; // DSR select
-wire drr_sel; // DRR select
-wire dvr0_sel,
- dvr1_sel,
- dvr2_sel,
- dvr3_sel,
- dvr4_sel,
- dvr5_sel,
- dvr6_sel,
- dvr7_sel; // DVR selects
-wire dcr0_sel,
- dcr1_sel,
- dcr2_sel,
- dcr3_sel,
- dcr4_sel,
- dcr5_sel,
- dcr6_sel,
- dcr7_sel; // DCR selects
-wire dwcr0_sel,
- dwcr1_sel; // DWCR selects
-reg dbg_bp_r;
-reg ex_freeze_q;
-`ifdef OR1200_DU_HWBKPTS
-reg [31:0] match_cond0_ct;
-reg [31:0] match_cond1_ct;
-reg [31:0] match_cond2_ct;
-reg [31:0] match_cond3_ct;
-reg [31:0] match_cond4_ct;
-reg [31:0] match_cond5_ct;
-reg [31:0] match_cond6_ct;
-reg [31:0] match_cond7_ct;
-reg match_cond0_stb;
-reg match_cond1_stb;
-reg match_cond2_stb;
-reg match_cond3_stb;
-reg match_cond4_stb;
-reg match_cond5_stb;
-reg match_cond6_stb;
-reg match_cond7_stb;
-reg match0;
-reg match1;
-reg match2;
-reg match3;
-reg match4;
-reg match5;
-reg match6;
-reg match7;
-reg wpcntr0_match;
-reg wpcntr1_match;
-reg incr_wpcntr0;
-reg incr_wpcntr1;
-reg [10:0] wp;
-`endif
-wire du_hwbkpt;
-reg du_hwbkpt_hold;
-`ifdef OR1200_DU_READREGS
-reg [31:0] spr_dat_o;
-`endif
-reg [13:0] except_stop; // Exceptions that stop because of DSR
-`ifdef OR1200_DU_TB_IMPLEMENTED
-wire tb_enw;
-reg [7:0] tb_wadr;
-reg [31:0] tb_timstmp;
-`endif
-wire [31:0] tbia_dat_o;
-wire [31:0] tbim_dat_o;
-wire [31:0] tbar_dat_o;
-wire [31:0] tbts_dat_o;
-
-//
-// DU registers address decoder
-//
-`ifdef OR1200_DU_DMR1
-assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
-`endif
-`ifdef OR1200_DU_DMR2
-assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
-`endif
-`ifdef OR1200_DU_DSR
-assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
-`endif
-`ifdef OR1200_DU_DRR
-assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
-`endif
-`ifdef OR1200_DU_DVR0
-assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
-`endif
-`ifdef OR1200_DU_DVR1
-assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
-`endif
-`ifdef OR1200_DU_DVR2
-assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
-`endif
-`ifdef OR1200_DU_DVR3
-assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
-`endif
-`ifdef OR1200_DU_DVR4
-assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
-`endif
-`ifdef OR1200_DU_DVR5
-assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
-`endif
-`ifdef OR1200_DU_DVR6
-assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
-`endif
-`ifdef OR1200_DU_DVR7
-assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
-`endif
-`ifdef OR1200_DU_DCR0
-assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
-`endif
-`ifdef OR1200_DU_DCR1
-assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
-`endif
-`ifdef OR1200_DU_DCR2
-assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
-`endif
-`ifdef OR1200_DU_DCR3
-assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
-`endif
-`ifdef OR1200_DU_DCR4
-assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
-`endif
-`ifdef OR1200_DU_DCR5
-assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
-`endif
-`ifdef OR1200_DU_DCR6
-assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
-`endif
-`ifdef OR1200_DU_DCR7
-assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
-`endif
-`ifdef OR1200_DU_DWCR0
-assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
-`endif
-`ifdef OR1200_DU_DWCR1
-assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
-`endif
-
-// Track previous ex_freeze to detect when signals are updated
-always @(posedge clk)
- ex_freeze_q <= ex_freeze;
-
-//
-// Decode started exception
-//
-// du_except_stop comes from or1200_except
-//
-always @(du_except_stop or ex_freeze_q) begin
- except_stop = 14'b00_0000_0000_0000;
- casez (du_except_stop)
- 14'b1?_????_????_????:
- except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
- 14'b01_????_????_????: begin
- except_stop[`OR1200_DU_DRR_IE] = 1'b1;
- end
- 14'b00_1???_????_????: begin
- except_stop[`OR1200_DU_DRR_IME] = 1'b1;
- end
- 14'b00_01??_????_????:
- except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
- 14'b00_001?_????_????: begin
- except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
- end
- 14'b00_0001_????_????:
- except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
- 14'b00_0000_1???_????: begin
- except_stop[`OR1200_DU_DRR_AE] = 1'b1;
- end
- 14'b00_0000_01??_????: begin
- except_stop[`OR1200_DU_DRR_DME] = 1'b1;
- end
- 14'b00_0000_001?_????:
- except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
- 14'b00_0000_0001_????:
- except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
- 14'b00_0000_0000_1???: begin
- except_stop[`OR1200_DU_DRR_RE] = 1'b1;
- end
- 14'b00_0000_0000_01??: begin
- except_stop[`OR1200_DU_DRR_TE] = 1'b1 & ~ex_freeze_q;
- end
- 14'b00_0000_0000_001?: begin
- except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
- end
- 14'b00_0000_0000_0001:
- except_stop[`OR1200_DU_DRR_SCE] = 1'b1 & ~ex_freeze_q;
- default:
- except_stop = 14'b00_0000_0000_0000;
- endcase // casez (du_except_stop)
-end
-
-//
-// dbg_bp_o is registered
-//
-assign dbg_bp_o = dbg_bp_r;
-
-//
-// Breakpoint activation register
-//
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dbg_bp_r <= 1'b0;
- else if (!ex_freeze)
- dbg_bp_r <= |except_stop
-`ifdef OR1200_DU_DMR1_ST
- | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
-`endif
-`ifdef OR1200_DU_DMR1_BT
- | (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
-`endif
- ;
- else
- dbg_bp_r <= |except_stop;
-
-//
-// Write to DMR1
-//
-`ifdef OR1200_DU_DMR1
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dmr1 <= 25'h000_0000;
- else if (dmr1_sel && spr_write)
-`ifdef OR1200_DU_HWBKPTS
- dmr1 <= spr_dat_i[24:0];
-`else
- dmr1 <= {1'b0, spr_dat_i[23:22], 22'h00_0000};
-`endif
-`else
-assign dmr1 = 25'h000_0000;
-`endif
-
-//
-// Write to DMR2
-//
-`ifdef OR1200_DU_DMR2
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dmr2 <= 24'h00_0000;
- else if (dmr2_sel && spr_write)
- dmr2 <= spr_dat_i[23:0];
-`else
-assign dmr2 = 24'h00_0000;
-`endif
-
-//
-// Write to DSR
-//
-`ifdef OR1200_DU_DSR
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
- else if (dsr_sel && spr_write)
- dsr <= spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
-`else
-assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
-`endif
-
-//
-// Write to DRR
-//
-`ifdef OR1200_DU_DRR
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- drr <= 14'b0;
- else if (drr_sel && spr_write)
- drr <= spr_dat_i[13:0];
- else
- drr <= drr | except_stop;
-`else
-assign drr = 14'b0;
-`endif
-
-//
-// Write to DVR0
-//
-`ifdef OR1200_DU_DVR0
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr0 <= 32'h0000_0000;
- else if (dvr0_sel && spr_write)
- dvr0 <= spr_dat_i[31:0];
-`else
-assign dvr0 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR1
-//
-`ifdef OR1200_DU_DVR1
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr1 <= 32'h0000_0000;
- else if (dvr1_sel && spr_write)
- dvr1 <= spr_dat_i[31:0];
-`else
-assign dvr1 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR2
-//
-`ifdef OR1200_DU_DVR2
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr2 <= 32'h0000_0000;
- else if (dvr2_sel && spr_write)
- dvr2 <= spr_dat_i[31:0];
-`else
-assign dvr2 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR3
-//
-`ifdef OR1200_DU_DVR3
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr3 <= 32'h0000_0000;
- else if (dvr3_sel && spr_write)
- dvr3 <= spr_dat_i[31:0];
-`else
-assign dvr3 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR4
-//
-`ifdef OR1200_DU_DVR4
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr4 <= 32'h0000_0000;
- else if (dvr4_sel && spr_write)
- dvr4 <= spr_dat_i[31:0];
-`else
-assign dvr4 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR5
-//
-`ifdef OR1200_DU_DVR5
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr5 <= 32'h0000_0000;
- else if (dvr5_sel && spr_write)
- dvr5 <= spr_dat_i[31:0];
-`else
-assign dvr5 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR6
-//
-`ifdef OR1200_DU_DVR6
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr6 <= 32'h0000_0000;
- else if (dvr6_sel && spr_write)
- dvr6 <= spr_dat_i[31:0];
-`else
-assign dvr6 = 32'h0000_0000;
-`endif
-
-//
-// Write to DVR7
-//
-`ifdef OR1200_DU_DVR7
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dvr7 <= 32'h0000_0000;
- else if (dvr7_sel && spr_write)
- dvr7 <= spr_dat_i[31:0];
-`else
-assign dvr7 = 32'h0000_0000;
-`endif
-
-//
-// Write to DCR0
-//
-`ifdef OR1200_DU_DCR0
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr0 <= 8'h00;
- else if (dcr0_sel && spr_write)
- dcr0 <= spr_dat_i[7:0];
-`else
-assign dcr0 = 8'h00;
-`endif
-
-//
-// Write to DCR1
-//
-`ifdef OR1200_DU_DCR1
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr1 <= 8'h00;
- else if (dcr1_sel && spr_write)
- dcr1 <= spr_dat_i[7:0];
-`else
-assign dcr1 = 8'h00;
-`endif
-
-//
-// Write to DCR2
-//
-`ifdef OR1200_DU_DCR2
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr2 <= 8'h00;
- else if (dcr2_sel && spr_write)
- dcr2 <= spr_dat_i[7:0];
-`else
-assign dcr2 = 8'h00;
-`endif
-
-//
-// Write to DCR3
-//
-`ifdef OR1200_DU_DCR3
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr3 <= 8'h00;
- else if (dcr3_sel && spr_write)
- dcr3 <= spr_dat_i[7:0];
-`else
-assign dcr3 = 8'h00;
-`endif
-
-//
-// Write to DCR4
-//
-`ifdef OR1200_DU_DCR4
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr4 <= 8'h00;
- else if (dcr4_sel && spr_write)
- dcr4 <= spr_dat_i[7:0];
-`else
-assign dcr4 = 8'h00;
-`endif
-
-//
-// Write to DCR5
-//
-`ifdef OR1200_DU_DCR5
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr5 <= 8'h00;
- else if (dcr5_sel && spr_write)
- dcr5 <= spr_dat_i[7:0];
-`else
-assign dcr5 = 8'h00;
-`endif
-
-//
-// Write to DCR6
-//
-`ifdef OR1200_DU_DCR6
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr6 <= 8'h00;
- else if (dcr6_sel && spr_write)
- dcr6 <= spr_dat_i[7:0];
-`else
-assign dcr6 = 8'h00;
-`endif
-
-//
-// Write to DCR7
-//
-`ifdef OR1200_DU_DCR7
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dcr7 <= 8'h00;
- else if (dcr7_sel && spr_write)
- dcr7 <= spr_dat_i[7:0];
-`else
-assign dcr7 = 8'h00;
-`endif
-
-//
-// Write to DWCR0
-//
-`ifdef OR1200_DU_DWCR0
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dwcr0 <= 32'h0000_0000;
- else if (dwcr0_sel && spr_write)
- dwcr0 <= spr_dat_i[31:0];
- else if (incr_wpcntr0)
- dwcr0[`OR1200_DU_DWCR_COUNT] <= dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
-`else
-assign dwcr0 = 32'h0000_0000;
-`endif
-
-//
-// Write to DWCR1
-//
-`ifdef OR1200_DU_DWCR1
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- dwcr1 <= 32'h0000_0000;
- else if (dwcr1_sel && spr_write)
- dwcr1 <= spr_dat_i[31:0];
- else if (incr_wpcntr1)
- dwcr1[`OR1200_DU_DWCR_COUNT] <= dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
-`else
-assign dwcr1 = 32'h0000_0000;
-`endif
-
-//
-// Read DU registers
-//
-`ifdef OR1200_DU_READREGS
-always @(spr_addr or dsr or drr or dmr1 or dmr2
- or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
- or dvr5 or dvr6 or dvr7
- or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
- or dcr5 or dcr6 or dcr7
- or dwcr0 or dwcr1
-`ifdef OR1200_DU_TB_IMPLEMENTED
- or tb_wadr or tbia_dat_o or tbim_dat_o
- or tbar_dat_o or tbts_dat_o
-`endif
- )
- casez (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
-`ifdef OR1200_DU_DVR0
- `OR1200_DU_DVR0:
- spr_dat_o = dvr0;
-`endif
-`ifdef OR1200_DU_DVR1
- `OR1200_DU_DVR1:
- spr_dat_o = dvr1;
-`endif
-`ifdef OR1200_DU_DVR2
- `OR1200_DU_DVR2:
- spr_dat_o = dvr2;
-`endif
-`ifdef OR1200_DU_DVR3
- `OR1200_DU_DVR3:
- spr_dat_o = dvr3;
-`endif
-`ifdef OR1200_DU_DVR4
- `OR1200_DU_DVR4:
- spr_dat_o = dvr4;
-`endif
-`ifdef OR1200_DU_DVR5
- `OR1200_DU_DVR5:
- spr_dat_o = dvr5;
-`endif
-`ifdef OR1200_DU_DVR6
- `OR1200_DU_DVR6:
- spr_dat_o = dvr6;
-`endif
-`ifdef OR1200_DU_DVR7
- `OR1200_DU_DVR7:
- spr_dat_o = dvr7;
-`endif
-`ifdef OR1200_DU_DCR0
- `OR1200_DU_DCR0:
- spr_dat_o = {24'h00_0000, dcr0};
-`endif
-`ifdef OR1200_DU_DCR1
- `OR1200_DU_DCR1:
- spr_dat_o = {24'h00_0000, dcr1};
-`endif
-`ifdef OR1200_DU_DCR2
- `OR1200_DU_DCR2:
- spr_dat_o = {24'h00_0000, dcr2};
-`endif
-`ifdef OR1200_DU_DCR3
- `OR1200_DU_DCR3:
- spr_dat_o = {24'h00_0000, dcr3};
-`endif
-`ifdef OR1200_DU_DCR4
- `OR1200_DU_DCR4:
- spr_dat_o = {24'h00_0000, dcr4};
-`endif
-`ifdef OR1200_DU_DCR5
- `OR1200_DU_DCR5:
- spr_dat_o = {24'h00_0000, dcr5};
-`endif
-`ifdef OR1200_DU_DCR6
- `OR1200_DU_DCR6:
- spr_dat_o = {24'h00_0000, dcr6};
-`endif
-`ifdef OR1200_DU_DCR7
- `OR1200_DU_DCR7:
- spr_dat_o = {24'h00_0000, dcr7};
-`endif
-`ifdef OR1200_DU_DMR1
- `OR1200_DU_DMR1:
- spr_dat_o = {7'h00, dmr1};
-`endif
-`ifdef OR1200_DU_DMR2
- `OR1200_DU_DMR2:
- spr_dat_o = {8'h00, dmr2};
-`endif
-`ifdef OR1200_DU_DWCR0
- `OR1200_DU_DWCR0:
- spr_dat_o = dwcr0;
-`endif
-`ifdef OR1200_DU_DWCR1
- `OR1200_DU_DWCR1:
- spr_dat_o = dwcr1;
-`endif
-`ifdef OR1200_DU_DSR
- `OR1200_DU_DSR:
- spr_dat_o = {18'b0, dsr};
-`endif
-`ifdef OR1200_DU_DRR
- `OR1200_DU_DRR:
- spr_dat_o = {18'b0, drr};
-`endif
-`ifdef OR1200_DU_TB_IMPLEMENTED
- `OR1200_DU_TBADR:
- spr_dat_o = {24'h000000, tb_wadr};
- `OR1200_DU_TBIA:
- spr_dat_o = tbia_dat_o;
- `OR1200_DU_TBIM:
- spr_dat_o = tbim_dat_o;
- `OR1200_DU_TBAR:
- spr_dat_o = tbar_dat_o;
- `OR1200_DU_TBTS:
- spr_dat_o = tbts_dat_o;
-`endif
- default:
- spr_dat_o = 32'h0000_0000;
- endcase
-`endif
-
-//
-// DSR alias
-//
-assign du_dsr = dsr;
-
-`ifdef OR1200_DU_HWBKPTS
-
-//
-// Compare To What (Match Condition 0)
-//
-always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond0_ct = id_pc; // insn fetch EA
- 3'b010: match_cond0_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond0_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond0_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond0_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond0_ct = dcpu_adr_i; // load/store EA
- default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 0)
-//
-always @(dcr0 or dcpu_cycstb_i)
- case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond0_stb = 1'b0; //comparison disabled
- 3'b001: match_cond0_stb = 1'b1; // insn fetch EA
- default:match_cond0_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 0
-//
-always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
- casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match0 = 1'b0;
- 4'b1_001: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} ==
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_010: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_011: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <=
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_100: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_101: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >=
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- 4'b1_110: match0 =
- ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} !=
- {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
- endcase
-
-//
-// Watchpoint 0
-//
-always @(dmr1 or match0)
- case (dmr1[`OR1200_DU_DMR1_CW0])
- 2'b00: wp[0] = match0;
- 2'b01: wp[0] = match0;
- 2'b10: wp[0] = match0;
- 2'b11: wp[0] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 1)
-//
-always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond1_ct = id_pc; // insn fetch EA
- 3'b010: match_cond1_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond1_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond1_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond1_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond1_ct = dcpu_adr_i; // load/store EA
- default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 1)
-//
-always @(dcr1 or dcpu_cycstb_i)
- case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond1_stb = 1'b0; //comparison disabled
- 3'b001: match_cond1_stb = 1'b1; // insn fetch EA
- default:match_cond1_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 1
-//
-always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
- casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match1 = 1'b0;
- 4'b1_001: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} ==
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_010: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_011: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <=
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_100: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_101: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >=
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- 4'b1_110: match1 =
- ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} !=
- {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
- endcase
-
-//
-// Watchpoint 1
-//
-always @(dmr1 or match1 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW1])
- 2'b00: wp[1] = match1;
- 2'b01: wp[1] = match1 & wp[0];
- 2'b10: wp[1] = match1 | wp[0];
- 2'b11: wp[1] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 2)
-//
-always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond2_ct = id_pc; // insn fetch EA
- 3'b010: match_cond2_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond2_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond2_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond2_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond2_ct = dcpu_adr_i; // load/store EA
- default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 2)
-//
-always @(dcr2 or dcpu_cycstb_i)
- case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond2_stb = 1'b0; //comparison disabled
- 3'b001: match_cond2_stb = 1'b1; // insn fetch EA
- default:match_cond2_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 2
-//
-always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
- casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match2 = 1'b0;
- 4'b1_001: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} ==
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_010: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_011: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <=
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_100: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_101: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >=
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- 4'b1_110: match2 =
- ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} !=
- {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
- endcase
-
-//
-// Watchpoint 2
-//
-always @(dmr1 or match2 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW2])
- 2'b00: wp[2] = match2;
- 2'b01: wp[2] = match2 & wp[1];
- 2'b10: wp[2] = match2 | wp[1];
- 2'b11: wp[2] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 3)
-//
-always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond3_ct = id_pc; // insn fetch EA
- 3'b010: match_cond3_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond3_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond3_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond3_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond3_ct = dcpu_adr_i; // load/store EA
- default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 3)
-//
-always @(dcr3 or dcpu_cycstb_i)
- case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond3_stb = 1'b0; //comparison disabled
- 3'b001: match_cond3_stb = 1'b1; // insn fetch EA
- default:match_cond3_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 3
-//
-always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
- casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match3 = 1'b0;
- 4'b1_001: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} ==
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_010: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_011: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <=
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_100: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_101: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >=
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- 4'b1_110: match3 =
- ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} !=
- {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
- endcase
-
-//
-// Watchpoint 3
-//
-always @(dmr1 or match3 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW3])
- 2'b00: wp[3] = match3;
- 2'b01: wp[3] = match3 & wp[2];
- 2'b10: wp[3] = match3 | wp[2];
- 2'b11: wp[3] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 4)
-//
-always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond4_ct = id_pc; // insn fetch EA
- 3'b010: match_cond4_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond4_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond4_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond4_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond4_ct = dcpu_adr_i; // load/store EA
- default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 4)
-//
-always @(dcr4 or dcpu_cycstb_i)
- case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond4_stb = 1'b0; //comparison disabled
- 3'b001: match_cond4_stb = 1'b1; // insn fetch EA
- default:match_cond4_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 4
-//
-always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
- casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match4 = 1'b0;
- 4'b1_001: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} ==
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_010: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_011: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <=
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_100: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_101: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >=
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- 4'b1_110: match4 =
- ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} !=
- {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
- endcase
-
-//
-// Watchpoint 4
-//
-always @(dmr1 or match4 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW4])
- 2'b00: wp[4] = match4;
- 2'b01: wp[4] = match4 & wp[3];
- 2'b10: wp[4] = match4 | wp[3];
- 2'b11: wp[4] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 5)
-//
-always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond5_ct = id_pc; // insn fetch EA
- 3'b010: match_cond5_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond5_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond5_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond5_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond5_ct = dcpu_adr_i; // load/store EA
- default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 5)
-//
-always @(dcr5 or dcpu_cycstb_i)
- case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond5_stb = 1'b0; //comparison disabled
- 3'b001: match_cond5_stb = 1'b1; // insn fetch EA
- default:match_cond5_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 5
-//
-always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
- casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match5 = 1'b0;
- 4'b1_001: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} ==
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_010: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_011: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <=
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_100: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_101: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >=
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- 4'b1_110: match5 =
- ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} !=
- {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
- endcase
-
-//
-// Watchpoint 5
-//
-always @(dmr1 or match5 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW5])
- 2'b00: wp[5] = match5;
- 2'b01: wp[5] = match5 & wp[4];
- 2'b10: wp[5] = match5 | wp[4];
- 2'b11: wp[5] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 6)
-//
-always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond6_ct = id_pc; // insn fetch EA
- 3'b010: match_cond6_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond6_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond6_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond6_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond6_ct = dcpu_adr_i; // load/store EA
- default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 6)
-//
-always @(dcr6 or dcpu_cycstb_i)
- case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond6_stb = 1'b0; //comparison disabled
- 3'b001: match_cond6_stb = 1'b1; // insn fetch EA
- default:match_cond6_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 6
-//
-always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
- casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match6 = 1'b0;
- 4'b1_001: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} ==
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_010: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_011: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <=
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_100: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_101: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >=
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- 4'b1_110: match6 =
- ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} !=
- {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
- endcase
-
-//
-// Watchpoint 6
-//
-always @(dmr1 or match6 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW6])
- 2'b00: wp[6] = match6;
- 2'b01: wp[6] = match6 & wp[5];
- 2'b10: wp[6] = match6 | wp[5];
- 2'b11: wp[6] = 1'b0;
- endcase
-
-//
-// Compare To What (Match Condition 7)
-//
-always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
- or dcpu_dat_lsu or dcpu_we_i)
- case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b001: match_cond7_ct = id_pc; // insn fetch EA
- 3'b010: match_cond7_ct = dcpu_adr_i; // load EA
- 3'b011: match_cond7_ct = dcpu_adr_i; // store EA
- 3'b100: match_cond7_ct = dcpu_dat_dc; // load data
- 3'b101: match_cond7_ct = dcpu_dat_lsu; // store data
- 3'b110: match_cond7_ct = dcpu_adr_i; // load/store EA
- default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
- endcase
-
-//
-// When To Compare (Match Condition 7)
-//
-always @(dcr7 or dcpu_cycstb_i)
- case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
- 3'b000: match_cond7_stb = 1'b0; //comparison disabled
- 3'b001: match_cond7_stb = 1'b1; // insn fetch EA
- default:match_cond7_stb = dcpu_cycstb_i; // any load/store
- endcase
-
-//
-// Match Condition 7
-//
-always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
- casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
- 4'b0_xxx,
- 4'b1_000,
- 4'b1_111: match7 = 1'b0;
- 4'b1_001: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} ==
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_010: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_011: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <=
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_100: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_101: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >=
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- 4'b1_110: match7 =
- ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} !=
- {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
- endcase
-
-//
-// Watchpoint 7
-//
-always @(dmr1 or match7 or wp)
- case (dmr1[`OR1200_DU_DMR1_CW7])
- 2'b00: wp[7] = match7;
- 2'b01: wp[7] = match7 & wp[6];
- 2'b10: wp[7] = match7 | wp[6];
- 2'b11: wp[7] = 1'b0;
- endcase
-
-//
-// Increment Watchpoint Counter 0
-//
-always @(wp or dmr2)
- if (dmr2[`OR1200_DU_DMR2_WCE0])
- incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
- else
- incr_wpcntr0 = 1'b0;
-
-//
-// Match Condition Watchpoint Counter 0
-//
-always @(dwcr0)
- if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
- wpcntr0_match = 1'b1;
- else
- wpcntr0_match = 1'b0;
-
-
-//
-// Watchpoint 8
-//
-always @(dmr1 or wpcntr0_match or wp)
- case (dmr1[`OR1200_DU_DMR1_CW8])
- 2'b00: wp[8] = wpcntr0_match;
- 2'b01: wp[8] = wpcntr0_match & wp[7];
- 2'b10: wp[8] = wpcntr0_match | wp[7];
- 2'b11: wp[8] = 1'b0;
- endcase
-
-
-//
-// Increment Watchpoint Counter 1
-//
-always @(wp or dmr2)
- if (dmr2[`OR1200_DU_DMR2_WCE1])
- incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
- else
- incr_wpcntr1 = 1'b0;
-
-//
-// Match Condition Watchpoint Counter 1
-//
-always @(dwcr1)
- if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
- wpcntr1_match = 1'b1;
- else
- wpcntr1_match = 1'b0;
-
-//
-// Watchpoint 9
-//
-always @(dmr1 or wpcntr1_match or wp)
- case (dmr1[`OR1200_DU_DMR1_CW9])
- 2'b00: wp[9] = wpcntr1_match;
- 2'b01: wp[9] = wpcntr1_match & wp[8];
- 2'b10: wp[9] = wpcntr1_match | wp[8];
- 2'b11: wp[9] = 1'b0;
- endcase
-
-//
-// Watchpoint 10
-//
-always @(dmr1 or dbg_ewt_i or wp)
- case (dmr1[`OR1200_DU_DMR1_CW10])
- 2'b00: wp[10] = dbg_ewt_i;
- 2'b01: wp[10] = dbg_ewt_i & wp[9];
- 2'b10: wp[10] = dbg_ewt_i | wp[9];
- 2'b11: wp[10] = 1'b0;
- endcase
-
-`endif
-
-//
-// Watchpoints can cause trap exception
-//
-`ifdef OR1200_DU_HWBKPTS
-assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]) | du_hwbkpt_hold | (dbg_bp_r & ~dsr[`OR1200_DU_DSR_TE]);
-`else
-assign du_hwbkpt = 1'b0;
-`endif
-
-// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- du_hwbkpt_hold <= 1'b0;
- else if (du_hwbkpt & ex_freeze)
- du_hwbkpt_hold <= 1'b1;
- else if (!ex_freeze)
- du_hwbkpt_hold <= 1'b0;
-
-`ifdef OR1200_DU_TB_IMPLEMENTED
-//
-// Simple trace buffer
-// (right now hardcoded for Xilinx Virtex FPGAs)
-//
-// Stores last 256 instruction addresses, instruction
-// machine words and ALU results
-//
-
-//
-// Trace buffer write enable
-//
-assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
-
-//
-// Trace buffer write address pointer
-//
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- tb_wadr <= 8'h00;
- else if (tb_enw)
- tb_wadr <= tb_wadr + 8'd1;
-
-//
-// Free running counter (time stamp)
-//
-always @(posedge clk or `OR1200_RST_EVENT rst)
- if (rst == `OR1200_RST_VALUE)
- tb_timstmp <= 32'h00000000;
- else if (!dbg_bp_r)
- tb_timstmp <= tb_timstmp + 32'd1;
-
-//
-// Trace buffer RAMs
-//
-
-or1200_dpram_256x32 tbia_ram(
- .clk_a(clk),
- .rst_a(1'b0),
- .addr_a(spr_addr[7:0]),
- .ce_a(1'b1),
- .oe_a(1'b1),
- .do_a(tbia_dat_o),
-
- .clk_b(clk),
- .rst_b(1'b0),
- .addr_b(tb_wadr),
- .di_b(spr_dat_npc),
- .ce_b(1'b1),
- .we_b(tb_enw)
-
-);
-
-or1200_dpram_256x32 tbim_ram(
- .clk_a(clk),
- .rst_a(1'b0),
- .addr_a(spr_addr[7:0]),
- .ce_a(1'b1),
- .oe_a(1'b1),
- .do_a(tbim_dat_o),
-
- .clk_b(clk),
- .rst_b(1'b0),
- .addr_b(tb_wadr),
- .di_b(ex_insn),
- .ce_b(1'b1),
- .we_b(tb_enw)
-);
-
-or1200_dpram_256x32 tbar_ram(
- .clk_a(clk),
- .rst_a(1'b0),
- .addr_a(spr_addr[7:0]),
- .ce_a(1'b1),
- .oe_a(1'b1),
- .do_a(tbar_dat_o),
-
- .clk_b(clk),
- .rst_b(1'b0),
- .addr_b(tb_wadr),
- .di_b(rf_dataw),
- .ce_b(1'b1),
- .we_b(tb_enw)
-);
-
-or1200_dpram_256x32 tbts_ram(
- .clk_a(clk),
- .rst_a(1'b0),
- .addr_a(spr_addr[7:0]),
- .ce_a(1'b1),
- .oe_a(1'b1),
- .do_a(tbts_dat_o),
-
- .clk_b(clk),
- .rst_b(1'b0),
- .addr_b(tb_wadr),
- .di_b(tb_timstmp),
- .ce_b(1'b1),
- .we_b(tb_enw)
-);
-
-`else
-
-assign tbia_dat_o = 32'h0000_0000;
-assign tbim_dat_o = 32'h0000_0000;
-assign tbar_dat_o = 32'h0000_0000;
-assign tbts_dat_o = 32'h0000_0000;
-
-`endif // OR1200_DU_TB_IMPLEMENTED
-
-`else // OR1200_DU_IMPLEMENTED
-
-//
-// When DU is not implemented, drive all outputs as would when DU is disabled
-//
-assign dbg_bp_o = 1'b0;
-assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
-assign du_dmr1 = {25{1'b0}};
-assign du_hwbkpt = 1'b0;
-
-//
-// Read DU registers
-//
-`ifdef OR1200_DU_READREGS
-assign spr_dat_o = 32'h0000_0000;
-`ifdef OR1200_DU_UNUSED_ZERO
-`endif
-`endif
-
-`endif
-
-endmodule
-
-
-
diff --git a/autotests/input/syntax/vhdl/light52_muldiv.vhdl b/autotests/input/syntax/vhdl/light52_muldiv.vhdl
deleted file mode 100644
index 723f1545..00000000
--- a/autotests/input/syntax/vhdl/light52_muldiv.vhdl
+++ /dev/null
@@ -1,239 +0,0 @@
---------------------------------------------------------------------------------
--- light52_muldiv.vhdl -- Simple multiplier/divider module.
---------------------------------------------------------------------------------
--- The 8051 mul and div instructions are both unsigned and operands are 8 bit.
---
--- This module implements the division as a sequential state machine which takes
--- 8 cycles to complete.
--- The multiplier can be implemented as sequential or as combinational, in which
--- case it will use a DSP block in those architectures that support it.
--- No attempt has been made to make this module generic or reusable.
---
--- If you want a combinational multiplier but don't want to waste a DSP block
--- in this module, you need to modify this file adding whatever synthesis
--- pragmas your tool of choice needs.
---
--- Note that unlike the division state machine, the combinational product logic
--- is always operating: when SEQUENTIAL_MULTIPLIER=true, prod_out equals
--- data_a * data_b with a latency of 1 clock cycle, and mul_ready is hardwired
--- to '1'.
---
--- FIXME explain division algorithm.
---------------------------------------------------------------------------------
--- GENERICS:
---
--- SEQUENTIAL_MULTIPLIER -- Sequential vs. combinational multiplier.
--- When true, a sequential implementation will be used for the multiplier,
--- which will usually save a lot of logic or a dedicated multiplier.
--- When false, a combinational registered multiplier will be used.
---
---------------------------------------------------------------------------------
--- INTERFACE SIGNALS:
---
--- clk : Clock, active rising edge.
--- reset : Synchronous reset. Clears only the control registers not
--- visible to the programmer -- not the output registers.
---
--- data_a : Numerator input, should be connected to the ACC register.
--- data_b : Denominator input, should be connected to the B register.
--- start : Assert for 1 cycle to start the division state machine
--- (and the product if SEQUENTIAL_MULTIPLIER=true);
---
--- prod_out : Product output, valid only when mul_ready='1'.
--- quot_out : Quotient output, valid only when div_ready='1'.
--- rem_out : Remainder output, valid only when div_ready='1'.
--- div_ov_out : Division overflow flag, valid only when div_ready='1'.
--- mul_ov_out : Product overflow flag, valid only when mul_ready='1'.
---
--- mul_ready : Asserted permanently if SEQUENTIAL_MULTIPLIER=false.
--- div_ready : Deasserted the cycle after start is asserted.
--- Asserted when the division has completed.
---
---------------------------------------------------------------------------------
--- Copyright (C) 2012 Jose A. Ruiz
---
--- This source file may be used and distributed without
--- restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains
--- the original copyright notice and the associated disclaimer.
---
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
---
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.opencores.org/lgpl.shtml
---------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.light52_pkg.all;
-use work.light52_ucode_pkg.all;
-
-entity light52_muldiv is
- generic (
- SEQUENTIAL_MULTIPLIER : boolean := false
- );
- port(
- clk : in std_logic;
- reset : in std_logic;
-
- data_a : in t_byte;
- data_b : in t_byte;
- start : in std_logic;
-
- prod_out : out t_word;
- quot_out : out t_byte;
- rem_out : out t_byte;
- div_ov_out : out std_logic;
- mul_ov_out : out std_logic;
-
- mul_ready : out std_logic;
- div_ready : out std_logic
- );
-end entity light52_muldiv;
-
-architecture sequential of light52_muldiv is
-
-signal bit_ctr : integer range 0 to 8;
-
-signal b_shift_reg : t_word;
-
-signal den_ge_256 : std_logic;
-signal num_ge_den : std_logic;
-signal sub_num : std_logic;
-
-signal denominator : t_byte;
-signal rem_reg : t_byte;
-signal quot_reg : t_byte;
-signal prod_reg : t_word;
-signal ready : std_logic;
-
-signal load_regs : std_logic;
-
-begin
-
--- Control logic ---------------------------------------------------------------
-
-control_counter: process(clk)
-begin
- if clk'event and clk='1' then
- if reset='1' then
- bit_ctr <= 8;
- else
- if load_regs='1' then
- bit_ctr <= 0;
- elsif bit_ctr /= 8 then
- bit_ctr <= bit_ctr + 1;
- end if;
- end if;
- end if;
-end process control_counter;
-
--- Internal signal ready is asserted after 8 cycles.
--- The sequential multiplier will use this signal too, IF it takes 8 cycles.
-
-ready <= '1' when bit_ctr >= 8 else '0';
-
-
----- Divider logic -------------------------------------------------------------
-
--- What we do is a simple base-2 'shift-and-subtract' algorithm that takes
--- 8 cycles to complete. We can get away with this because we deal with unsigned
--- numbers only.
-
-divider_registers: process(clk)
-begin
- if clk'event and clk='1' then
- -- denominator shift register
- if load_regs='1' then
- b_shift_reg <= "0" & data_b & "0000000";
- -- Division overflow can be determined upon loading B reg data.
- -- OV will be raised only on div-by-zero.
- if data_b=X"00" then
- div_ov_out <= '1';
- else
- div_ov_out <= '0';
- end if;
- else
- b_shift_reg <= "0" & b_shift_reg(b_shift_reg'high downto 1);
- end if;
-
- -- numerator register
- if load_regs='1' then
- rem_reg <= data_a;
- elsif bit_ctr/=8 and sub_num='1' then
- rem_reg <= rem_reg - denominator;
- end if;
-
- --- quotient register
- if load_regs='1' then
- quot_reg <= (others => '0');
- elsif bit_ctr/=8 then
- quot_reg <= quot_reg(quot_reg'high-1 downto 0) & sub_num;
- end if;
-
- load_regs <= start;
- end if;
-end process divider_registers;
-
-denominator <= b_shift_reg(7 downto 0);
-
--- The 16-bit comparison between b_shift_reg (denominator) and the zero-extended
--- rem_reg (numerator) can be simplified by splitting it in 2:
--- If the shifted denominator high byte is not zero, it is >=256...
-den_ge_256 <= '1' when b_shift_reg(15 downto 8) /= X"00" else '0';
--- ...otherwise we need to compare the low bytes.
-num_ge_den <= '1' when rem_reg >= denominator else '0';
-sub_num <= '1' when den_ge_256='0' and num_ge_den='1' else '0';
-
-
-quot_out <= quot_reg;
-prod_out <= prod_reg;
-rem_out <= rem_reg;
-
-div_ready <= ready;
-
----- Multiplier logic ----------------------------------------------------------
-
----- Combinational multiplier -----------------------------
-multiplier_combinational: if not SEQUENTIAL_MULTIPLIER generate
-
-registered_combinational_multiplier:process(clk)
-begin
- if clk'event and clk='1' then
- prod_reg <= data_a * data_b; -- t_byte is unsigned
- end if;
-end process registered_combinational_multiplier;
-
--- The multiplier output is valid in the cycle after the operands are loaded,
--- so by the time MUL is executed it's already done.
-mul_ready <= '1';
-
-mul_ov_out <= '1' when prod_reg(15 downto 8)/=X"00" else '0';
-prod_out <= prod_reg;
-
-end generate multiplier_combinational;
-
----- Sequential multiplier --------------------------------
-multiplier_sequential: if SEQUENTIAL_MULTIPLIER generate
-
-assert false
-report "Sequential multiplier implementation not done yet."&
- " Use combinational implementation."
-severity failure;
-
-end generate multiplier_sequential;
-
-end sequential;
diff --git a/autotests/input/syntax/vhdl/light52_tb.vhdl b/autotests/input/syntax/vhdl/light52_tb.vhdl
deleted file mode 100644
index 4905de10..00000000
--- a/autotests/input/syntax/vhdl/light52_tb.vhdl
+++ /dev/null
@@ -1,180 +0,0 @@
---------------------------------------------------------------------------------
--- light52_tb.vhdl --
---------------------------------------------------------------------------------
--- This test bench simulates the execution of some program (whose object code
--- is in package obj_code_pkg, in the form of a memory init constant) and logs
--- the execution to a text file called 'hw_sim_log.txt' (light52_tb_pkg.vhdl).
---
--- This test bench does no actual tests on the core. Instead, the simulation log
--- is meant to be matched against the simulation log produced by running the
--- same program on the software simulator B51 (also included with this project).
---
--- This will catch errors in the implementation of the CPU if the simulated
--- program has anough coverage -- the opcode tester is meant to cover all CPU
--- opcodes in many (not all) of their corner cases.
--- This scheme will not help in catching errors in the peripheral modules,
--- mainly because the current version of B51 does not simulate them.
---
---------------------------------------------------------------------------------
--- Copyright (C) 2012 Jose A. Ruiz
---
--- This source file may be used and distributed without
--- restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains
--- the original copyright notice and the associated disclaimer.
---
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
---
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.opencores.org/lgpl.shtml
---------------------------------------------------------------------------------
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use std.textio.all;
-
-use work.light52_pkg.all;
-use work.obj_code_pkg.all;
-use work.light52_tb_pkg.all;
-use work.txt_util.all;
-
-entity light52_tb is
-generic (BCD : boolean := true);
-end;
-
-
-architecture testbench of light52_tb is
-
---------------------------------------------------------------------------------
--- Simulation parameters
--- FIXME these should be in parameter package
-
--- Simulated clock period is the same as the usual target, the DE-1 board
-constant T : time := 20 ns; -- 50MHz
-constant SIMULATION_LENGTH : integer := 400000;
-
---------------------------------------------------------------------------------
--- MPU interface
-
-signal clk : std_logic := '0';
-signal reset : std_logic := '1';
-
-signal p0_out : std_logic_vector(7 downto 0);
-signal p1_out : std_logic_vector(7 downto 0);
-signal p2_in : std_logic_vector(7 downto 0);
-signal p3_in : std_logic_vector(7 downto 0);
-
-signal external_irq : std_logic_vector(7 downto 0);
-
-signal txd, rxd : std_logic;
-
---------------------------------------------------------------------------------
--- Logging signals & simulation control
-
--- Asserted high to disable the clock and terminate the simulation.
-signal done : std_logic := '0';
-
--- Log file
-file log_file: TEXT open write_mode is "hw_sim_log.txt";
--- Console output log file
-file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
--- Info record needed by the logging fuctions
-signal log_info : t_log_info;
-
-begin
-
----- UUT instantiation ---------------------------------------------------------
-
-uut: entity work.light52_mcu
- generic map (
- IMPLEMENT_BCD_INSTRUCTIONS => BCD,
- CODE_ROM_SIZE => work.obj_code_pkg.XCODE_SIZE,
- XDATA_RAM_SIZE => work.obj_code_pkg.XDATA_SIZE,
- OBJ_CODE => work.obj_code_pkg.object_code
- )
- port map (
- clk => clk,
- reset => reset,
-
- txd => txd,
- rxd => rxd,
-
- external_irq => external_irq,
-
- p0_out => p0_out,
- p1_out => p1_out,
- p2_in => p2_in,
- p3_in => p3_in
- );
-
- -- UART is looped back in the test bench.
- rxd <= txd;
-
- -- I/O ports are looped back and otherwise unused.
- p2_in <= p0_out;
- p3_in <= p1_out;
-
- -- External IRQ inputs are tied to port P1 for test purposes
- external_irq <= p1_out;
-
- ---- Master clock: free running clock used as main module clock ------------
- run_master_clock: process(done, clk)
- begin
- if done = '0' then
- clk <= not clk after T/2;
- end if;
- end process run_master_clock;
-
-
- ---- Main simulation process: reset MCU and wait for fixed period ----------
-
- drive_uut: process
- begin
- -- Leave reset asserted for a few clock cycles...
- reset <= '1';
- wait for T*4;
- reset <= '0';
-
- -- ...and wait for the test to hit a termination condition (evaluated by
- -- function log_cpu_activity) or to just timeout.
- wait for T*SIMULATION_LENGTH;
-
- -- If we arrive here, the simulation timed out (termination conditions
- -- trigger a failed assertion).
- -- So print a timeout message and quit.
- print("TB timed out.");
- done <= '1';
- wait;
-
- end process drive_uut;
-
-
- -- Logging process: launch logger functions --------------------------------
- log_execution: process
- begin
- -- Log cpu activity until done='1'.
- log_cpu_activity(clk, reset, done, "/uut",
- log_info, work.obj_code_pkg.XCODE_SIZE, "log_info",
- X"0000", log_file, con_file);
-
- -- Flush console log file when finished.
- log_flush_console(log_info, con_file);
-
- wait;
- end process log_execution;
-
-end architecture testbench;
diff --git a/autotests/input/syntax/vhdl/results/light52_muldiv.vhdl.reference.html b/autotests/input/syntax/vhdl/results/light52_muldiv.vhdl.reference.html
deleted file mode 100644
index af2fd1c7..00000000
--- a/autotests/input/syntax/vhdl/results/light52_muldiv.vhdl.reference.html
+++ /dev/null
@@ -1,253 +0,0 @@
-
-
-
-
-
-
-light52_muldiv.vhdl
-
-
-
-
---------------------------------------------------------------------------------
--- light52_muldiv.vhdl -- Simple multiplier/divider module.
---------------------------------------------------------------------------------
--- The 8051 mul and div instructions are both unsigned and operands are 8 bit.
---
--- This module implements the division as a sequential state machine which takes
--- 8 cycles to complete.
--- The multiplier can be implemented as sequential or as combinational, in which
--- case it will use a DSP block in those architectures that support it.
--- No attempt has been made to make this module generic or reusable.
---
--- If you want a combinational multiplier but don't want to waste a DSP block
--- in this module, you need to modify this file adding whatever synthesis
--- pragmas your tool of choice needs.
---
--- Note that unlike the division state machine, the combinational product logic
--- is always operating: when SEQUENTIAL_MULTIPLIER=true, prod_out equals
--- data_a * data_b with a latency of 1 clock cycle, and mul_ready is hardwired
--- to '1'.
---
--- FIXME explain division algorithm.
---------------------------------------------------------------------------------
--- GENERICS:
---
--- SEQUENTIAL_MULTIPLIER -- Sequential vs. combinational multiplier.
--- When true, a sequential implementation will be used for the multiplier,
--- which will usually save a lot of logic or a dedicated multiplier.
--- When false, a combinational registered multiplier will be used.
---
---------------------------------------------------------------------------------
--- INTERFACE SIGNALS:
---
--- clk : Clock, active rising edge.
--- reset : Synchronous reset. Clears only the control registers not
--- visible to the programmer -- not the output registers.
---
--- data_a : Numerator input, should be connected to the ACC register.
--- data_b : Denominator input, should be connected to the B register.
--- start : Assert for 1 cycle to start the division state machine
--- (and the product if SEQUENTIAL_MULTIPLIER=true);
---
--- prod_out : Product output, valid only when mul_ready='1'.
--- quot_out : Quotient output, valid only when div_ready='1'.
--- rem_out : Remainder output, valid only when div_ready='1'.
--- div_ov_out : Division overflow flag, valid only when div_ready='1'.
--- mul_ov_out : Product overflow flag, valid only when mul_ready='1'.
---
--- mul_ready : Asserted permanently if SEQUENTIAL_MULTIPLIER=false.
--- div_ready : Deasserted the cycle after start is asserted.
--- Asserted when the division has completed.
---
---------------------------------------------------------------------------------
--- Copyright (C) 2012 Jose A. Ruiz
---
--- This source file may be used and distributed without
--- restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains
--- the original copyright notice and the associated disclaimer.
---
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
---
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.opencores.org/lgpl.shtml
---------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.light52_pkg.all;
-use work.light52_ucode_pkg.all;
-
-entity light52_muldiv is
- generic (
- SEQUENTIAL_MULTIPLIER : boolean := false
- );
- port(
- clk : in std_logic;
- reset : in std_logic;
-
- data_a : in t_byte;
- data_b : in t_byte;
- start : in std_logic;
-
- prod_out : out t_word;
- quot_out : out t_byte;
- rem_out : out t_byte;
- div_ov_out : out std_logic;
- mul_ov_out : out std_logic;
-
- mul_ready : out std_logic;
- div_ready : out std_logic
- );
-end entity light52_muldiv;
-
-architecture sequential of light52_muldiv is
-
-signal bit_ctr : integer range 0 to 8;
-
-signal b_shift_reg : t_word;
-
-signal den_ge_256 : std_logic;
-signal num_ge_den : std_logic;
-signal sub_num : std_logic;
-
-signal denominator : t_byte;
-signal rem_reg : t_byte;
-signal quot_reg : t_byte;
-signal prod_reg : t_word;
-signal ready : std_logic;
-
-signal load_regs : std_logic;
-
-begin
-
--- Control logic ---------------------------------------------------------------
-
-control_counter: process(clk)
-begin
- if clk'event and clk='1' then
- if reset='1' then
- bit_ctr <= 8;
- else
- if load_regs='1' then
- bit_ctr <= 0;
- elsif bit_ctr /= 8 then
- bit_ctr <= bit_ctr + 1;
- end if;
- end if;
- end if;
-end process control_counter;
-
--- Internal signal ready is asserted after 8 cycles.
--- The sequential multiplier will use this signal too, IF it takes 8 cycles.
-
-ready <= '1' when bit_ctr >= 8 else '0';
-
-
----- Divider logic -------------------------------------------------------------
-
--- What we do is a simple base-2 'shift-and-subtract' algorithm that takes
--- 8 cycles to complete. We can get away with this because we deal with unsigned
--- numbers only.
-
-divider_registers: process(clk)
-begin
- if clk'event and clk='1' then
- -- denominator shift register
- if load_regs='1' then
- b_shift_reg <= "0" & data_b & "0000000";
- -- Division overflow can be determined upon loading B reg data.
- -- OV will be raised only on div-by-zero.
- if data_b=X"00" then
- div_ov_out <= '1';
- else
- div_ov_out <= '0';
- end if;
- else
- b_shift_reg <= "0" & b_shift_reg(b_shift_reg'high downto 1);
- end if;
-
- -- numerator register
- if load_regs='1' then
- rem_reg <= data_a;
- elsif bit_ctr/=8 and sub_num='1' then
- rem_reg <= rem_reg - denominator;
- end if;
-
- --- quotient register
- if load_regs='1' then
- quot_reg <= (others => '0');
- elsif bit_ctr/=8 then
- quot_reg <= quot_reg(quot_reg'high-1 downto 0) & sub_num;
- end if;
-
- load_regs <= start;
- end if;
-end process divider_registers;
-
-denominator <= b_shift_reg(7 downto 0);
-
--- The 16-bit comparison between b_shift_reg (denominator) and the zero-extended
--- rem_reg (numerator) can be simplified by splitting it in 2:
--- If the shifted denominator high byte is not zero, it is >=256...
-den_ge_256 <= '1' when b_shift_reg(15 downto 8) /= X"00" else '0';
--- ...otherwise we need to compare the low bytes.
-num_ge_den <= '1' when rem_reg >= denominator else '0';
-sub_num <= '1' when den_ge_256='0' and num_ge_den='1' else '0';
-
-
-quot_out <= quot_reg;
-prod_out <= prod_reg;
-rem_out <= rem_reg;
-
-div_ready <= ready;
-
----- Multiplier logic ----------------------------------------------------------
-
----- Combinational multiplier -----------------------------
-multiplier_combinational: if not SEQUENTIAL_MULTIPLIER generate
-
-registered_combinational_multiplier:process(clk)
-begin
- if clk'event and clk='1' then
- prod_reg <= data_a * data_b; -- t_byte is unsigned
- end if;
-end process registered_combinational_multiplier;
-
--- The multiplier output is valid in the cycle after the operands are loaded,
--- so by the time MUL is executed it's already done.
-mul_ready <= '1';
-
-mul_ov_out <= '1' when prod_reg(15 downto 8)/=X"00" else '0';
-prod_out <= prod_reg;
-
-end generate multiplier_combinational;
-
----- Sequential multiplier --------------------------------
-multiplier_sequential: if SEQUENTIAL_MULTIPLIER generate
-
-assert false
-report "Sequential multiplier implementation not done yet."&
- " Use combinational implementation."
-severity failure;
-
-end generate multiplier_sequential;
-
-end sequential;
-
-
-
diff --git a/autotests/input/syntax/vhdl/results/light52_tb.vhdl.reference.html b/autotests/input/syntax/vhdl/results/light52_tb.vhdl.reference.html
deleted file mode 100644
index 20a6209d..00000000
--- a/autotests/input/syntax/vhdl/results/light52_tb.vhdl.reference.html
+++ /dev/null
@@ -1,194 +0,0 @@
-
-
-
-
-
-
-light52_tb.vhdl
-
-
-
-
---------------------------------------------------------------------------------
--- light52_tb.vhdl --
---------------------------------------------------------------------------------
--- This test bench simulates the execution of some program (whose object code
--- is in package obj_code_pkg, in the form of a memory init constant) and logs
--- the execution to a text file called 'hw_sim_log.txt' (light52_tb_pkg.vhdl).
---
--- This test bench does no actual tests on the core. Instead, the simulation log
--- is meant to be matched against the simulation log produced by running the
--- same program on the software simulator B51 (also included with this project).
---
--- This will catch errors in the implementation of the CPU if the simulated
--- program has anough coverage -- the opcode tester is meant to cover all CPU
--- opcodes in many (not all) of their corner cases.
--- This scheme will not help in catching errors in the peripheral modules,
--- mainly because the current version of B51 does not simulate them.
---
---------------------------------------------------------------------------------
--- Copyright (C) 2012 Jose A. Ruiz
---
--- This source file may be used and distributed without
--- restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains
--- the original copyright notice and the associated disclaimer.
---
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
---
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.opencores.org/lgpl.shtml
---------------------------------------------------------------------------------
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use std.textio.all;
-
-use work.light52_pkg.all;
-use work.obj_code_pkg.all;
-use work.light52_tb_pkg.all;
-use work.txt_util.all;
-
-entity light52_tb is
-generic (BCD : boolean := true);
-end;
-
-
-architecture testbench of light52_tb is
-
---------------------------------------------------------------------------------
--- Simulation parameters
--- FIXME these should be in parameter package
-
--- Simulated clock period is the same as the usual target, the DE-1 board
-constant T : time := 20 ns; -- 50MHz
-constant SIMULATION_LENGTH : integer := 400000;
-
---------------------------------------------------------------------------------
--- MPU interface
-
-signal clk : std_logic := '0';
-signal reset : std_logic := '1';
-
-signal p0_out : std_logic_vector(7 downto 0);
-signal p1_out : std_logic_vector(7 downto 0);
-signal p2_in : std_logic_vector(7 downto 0);
-signal p3_in : std_logic_vector(7 downto 0);
-
-signal external_irq : std_logic_vector(7 downto 0);
-
-signal txd, rxd : std_logic;
-
---------------------------------------------------------------------------------
--- Logging signals & simulation control
-
--- Asserted high to disable the clock and terminate the simulation.
-signal done : std_logic := '0';
-
--- Log file
-file log_file: TEXT open write_mode is "hw_sim_log.txt";
--- Console output log file
-file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
--- Info record needed by the logging fuctions
-signal log_info : t_log_info;
-
-begin
-
----- UUT instantiation ---------------------------------------------------------
-
-uut: entity work.light52_mcu
- generic map (
- IMPLEMENT_BCD_INSTRUCTIONS => BCD,
- CODE_ROM_SIZE => work.obj_code_pkg.XCODE_SIZE,
- XDATA_RAM_SIZE => work.obj_code_pkg.XDATA_SIZE,
- OBJ_CODE => work.obj_code_pkg.object_code
- )
- port map (
- clk => clk,
- reset => reset,
-
- txd => txd,
- rxd => rxd,
-
- external_irq => external_irq,
-
- p0_out => p0_out,
- p1_out => p1_out,
- p2_in => p2_in,
- p3_in => p3_in
- );
-
- -- UART is looped back in the test bench.
- rxd <= txd;
-
- -- I/O ports are looped back and otherwise unused.
- p2_in <= p0_out;
- p3_in <= p1_out;
-
- -- External IRQ inputs are tied to port P1 for test purposes
- external_irq <= p1_out;
-
- ---- Master clock: free running clock used as main module clock ------------
- run_master_clock: process(done, clk)
- begin
- if done = '0' then
- clk <= not clk after T/2;
- end if;
- end process run_master_clock;
-
-
- ---- Main simulation process: reset MCU and wait for fixed period ----------
-
- drive_uut: process
- begin
- -- Leave reset asserted for a few clock cycles...
- reset <= '1';
- wait for T*4;
- reset <= '0';
-
- -- ...and wait for the test to hit a termination condition (evaluated by
- -- function log_cpu_activity) or to just timeout.
- wait for T*SIMULATION_LENGTH;
-
- -- If we arrive here, the simulation timed out (termination conditions
- -- trigger a failed assertion).
- -- So print a timeout message and quit.
- print("TB timed out.");
- done <= '1';
- wait;
-
- end process drive_uut;
-
-
- -- Logging process: launch logger functions --------------------------------
- log_execution: process
- begin
- -- Log cpu activity until done='1'.
- log_cpu_activity(clk, reset, done, "/uut",
- log_info, work.obj_code_pkg.XCODE_SIZE, "log_info",
- X"0000", log_file, con_file);
-
- -- Flush console log file when finished.
- log_flush_console(log_info, con_file);
-
- wait;
- end process log_execution;
-
-end architecture testbench;
-
-
-
diff --git a/autotests/src/katesyntaxtest.cpp b/autotests/src/katesyntaxtest.cpp
deleted file mode 100644
index 54db74e0..00000000
--- a/autotests/src/katesyntaxtest.cpp
+++ /dev/null
@@ -1,134 +0,0 @@
-/* This file is part of the Kate project.
- *
- * Copyright (C) 2013 Dominik Haumann
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Library General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Library General Public License for more details.
- *
- * You should have received a copy of the GNU Library General Public License
- * along with this library; see the file COPYING.LIB. If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA 02110-1301, USA.
- */
-
-#include "katesyntaxtest.h"
-
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-#include
-#include
-#include
-
-QTEST_MAIN(KateSyntaxTest)
-
-void KateSyntaxTest::initTestCase()
-{
- KTextEditor::EditorPrivate::enableUnitTestMode();
-}
-
-void KateSyntaxTest::cleanupTestCase()
-{
-}
-
-void KateSyntaxTest::testSyntaxHighlighting_data()
-{
- QTest::addColumn("hlTestCase");
-
- /**
- * check for directories, one dir == one hl
- */
- const QString testDir(QLatin1String(TEST_DATA_DIR) + QLatin1String("syntax/"));
- QDirIterator contents(testDir);
- while (contents.hasNext()) {
- const QString hlDir = contents.next();
- const QFileInfo info(hlDir);
- if (!info.isDir() || info.fileName().contains(QLatin1Char('.'))) {
- continue;
- }
-
- /**
- * now: get the tests per hl
- */
- QDirIterator contents(hlDir);
- while (contents.hasNext()) {
- const QString hlTestCase = contents.next();
- const QFileInfo info(hlTestCase);
- if (!info.isFile()) {
- continue;
- }
-
- QTest::newRow(info.absoluteFilePath().toLocal8Bit().constData()) << info.absoluteFilePath();
- }
- }
-}
-
-
-void KateSyntaxTest::testSyntaxHighlighting()
-{
- /**
- * get current test case
- */
- QFETCH(QString, hlTestCase);
-
- /**
- * create a document with a view to be able to export stuff
- */
- KTextEditor::DocumentPrivate doc;
- auto view = static_cast(doc.createView(nullptr));
-
- /**
- * load the test case
- * enforce UTF-8 to avoid locale problems
- */
- QUrl url;
- url.setScheme(QLatin1String("file"));
- url.setPath(hlTestCase);
- doc.setEncoding(QStringLiteral("UTF-8"));
- QVERIFY(doc.openUrl(url));
-
- /**
- * compute needed dirs
- */
- const QFileInfo info(hlTestCase);
- const QString resultDir(info.absolutePath() + QLatin1String("/results/"));
- const QString currentResult(resultDir + info.fileName() + QLatin1String(".current.html"));
- const QString referenceResult(resultDir + info.fileName() + QLatin1String(".reference.html"));
-
- /**
- * export the result
- */
- view->exportHtmlToFile(currentResult);
-
- /**
- * verify the result against reference
- */
- QProcess diff;
- diff.setProcessChannelMode(QProcess::MergedChannels);
- QStringList args;
- args << QLatin1String("-u") << (referenceResult) << (currentResult);
- diff.start(QLatin1String("diff"), args);
- diff.waitForFinished();
- QByteArray out = diff.readAllStandardOutput();
- if (!out.isEmpty()) {
- printf("DIFF:\n");
- QList outLines = out.split('\n');
- Q_FOREACH(const QByteArray &line, outLines) {
- printf("%s\n", qPrintable(line));
- }
- }
- QCOMPARE(QString::fromLocal8Bit(out), QString());
- QCOMPARE(diff.exitCode(), EXIT_SUCCESS);
-}
diff --git a/autotests/src/katesyntaxtest.h b/autotests/src/katesyntaxtest.h
deleted file mode 100644
index 2e3348be..00000000
--- a/autotests/src/katesyntaxtest.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* This file is part of the KDE libraries
- Copyright (C) 2013 Dominik Haumann
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Library General Public
- License as published by the Free Software Foundation; either
- version 2 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Library General Public License for more details.
-
- You should have received a copy of the GNU Library General Public License
- along with this library; see the file COPYING.LIB. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA.
-*/
-
-#ifndef KATE_SYNTAX_TEST_H
-#define KATE_SYNTAX_TEST_H
-
-#include
-
-class KateSyntaxTest : public QObject
-{
- Q_OBJECT
-
-public Q_SLOTS:
- void initTestCase();
- void cleanupTestCase();
-
-private Q_SLOTS:
- void testSyntaxHighlighting_data();
- void testSyntaxHighlighting();
-};
-
-#endif // KATE_FOLDING_TEST_H